Bill Lemmer Email & Phone Number

RFIC layout experience on 40nm & 65nm RF + Base Band WiMAX system-on-chip. Use of Cadence & Mentor layout tools, PVS & Calibre verification.

Layout of 40nm, 8 metal Receiver and Transmitter including floor planning and cell layout. Assign layout work to other contract layout personal and deliver completed top-level blocks. Knowledgeable of special DFM and regular DRC rules as applies to 40nm process. Responsible for top-level layout and floor planning of JEDEC DDR3 Memory Interface. Including.

RFIC layout experience for WIFI chip. Layout of LNA’s, PA’s, mixers, PLL, VCO, Reference Oscillators, regulators, padring, and bias circuits. Use of Cadence Layout, Verification, and Voltage Storm IR drop and EM tools. Top-level and cell level VCAR routing experience.

Lead layout designer for 90nm CMOS Multi-gigabit Transceiver. Responsibilities include: top-level floor planning, analog and digital layout, LVS, DRC, ERC, XOR’s and delivering the top-level block to the FPGA integration team. Layouts completed included PLL’s, ESD, clocks, line driver and bias circuits. Experienced at assigning layout responsibilities to.

Contract employee responsible for layout of mixed signal IC's for medical pacemakers using multi metal 1.5um and single metal 3.0um CMOS processes. Blocks included sense amp, ESD devices, and custom digital blocks.

Lead layout designer on Battery Management and Real-Time Clock Integrated Circuits.

Amps and Government Military products

Contractor working on Micro Processors used in GM vehicles.Computer Cadence: Virtuoso & Virtuoso XL, Schematic Composer, VCR router, AssuraSkills Verification tools, Voltage Storm, Calibre Verification tools, Synchronicity, Word, Excel

Associates Degree

Associates Degree, Mechanical Drafting