Bo-Chun Chen Email & Phone Number

Pittsburgh, Pa, Us

Hsinchu City, Taiwan, Taiwan

1. Computer Aided Design Software Tools Development for CXL/PCIE Memory Controller. (Python)– Developed RTL checker in Python using OOP paradigm to averagely reduce 70% of RTL errors in a project by building 30+ customized checking rules, and further secured the correctness and sped up the code reconstruction by 50% via establishing 30+ unit tests within Python Unittest Framework.– Used YAML format to interface with other automatic programs, and used Git and GitLab for version control.2. RTL and u-Architecture Design for Multiple Memory Controller Projects. (Verilog/SystemVerilog)– Developed the u-architecture and RTL of a Transaction Layer than can convert parallel CXL3.1messages into multiple AMBA CXS protocols.– Developed the u-architecture and RTL of a Transaction Layer than can convert CXL3.1 messages into Intel CPI 1.0 standard and Xilinx native DDR4 APP standard.– Developed the u-architecture and RTL of an NVME-oC Bridge to realize reducing unnecessary data movement between host and device, achieving the granularity of 64B rather than standard 4KB.

Hsinchu

2019 performance review : I+ (exceed expectation)1.Automatic Software Tools Development for 4G-LTE and 5G-NR Mobile Phone Applications. (Perl, TCL)– Developed 5+ Perl scripts to integrate XDC tool codes and error-checking mechanism into the Perforce platform using OOP design pattern, resolving 200 implicit potential glitches in a project on average, and sped up the tool check closure by 80%.– Established 20+ functions and 2 traversing algorithms in TCL scripts, and further enveloped them as a central library that can be called by users to automatically set up SDC for authorized IPs in projects.2. RTL Design and Sub-System Integration for 4G-LTE and 5G-NR Mobile Phone Applications. (Verilog)– Developed 7 new IPs in Verilog to address problems covering asynchronous bridges, synchronous slicing, arbitration, idle protection, and BIST for transition faults between sub-systems that helped drop 200 dppm within only 400 cycles and cost of 19.5k (um*um) (TSMC 10nm).– Led a top module team for developing debugging mechanism, Watch Dog Reset system, and interrupt generating unit to reduce 90% of user’s time in debugging with adding their own auxiliary signals.– Integrated 30+ GALS AXI4.0, GALS AHB3.0, APB3.0 asynchronous interfaces and clock controller unit in infra system to reach the peripheral requests from projects.

Hsinchu, Taiwan

2015 performance review : I+ (exceed expectation)2016 performance review : I+ (exceed expectation)

Taipei, Taiwan

Modern Filter Theory and Design

Master Of Science - Ms, Computer Vision

School of Computer Science Robotics Institute Master of Science in Computer Vision Coursework: 10601 Machine Learning 16820 Advanced.

Master'S Degree, Graduate Institute Of Electronic Engineering, Ics, Gpa : 4.17/4.3

Thesis : Real-time Eye Localization, Eye Blinking Detection, and Gaze Detection System without Infrared Illumination ●Ranked 1st in 101-2.

Bachelor'S Degree, Electronics Engineering, Gpa : 3.58/4.3