Bob Mcauliffe Email & Phone Number

Fort Collins, Co, Us

I am currently doing contract work as a Design Verification engineer and Project lead but am open to new opportunities. During the last few years I have been working primarily as a verification engineer, but I also have extensive experience in digital design. This experience spans gate-level logic design, PC board design, FPGA-based design, and RTL design targeted to ASICs and SOCs.My verification experience includes development of UVM-based components and testbenches. I also have extensive experience implementing class-based, object-oriented testbenches using System Verilog. I am a proponent of coverage-driven verification methodologies and have developed formal testplans and coverage models.

Santa Clara, Ca, Us

In this role I managed three verification engineers and also did a great deal of technical work. Projects included HDD and SDD controller SOCs. My group developed UVM testbenches, coverage models, and testcases for these ARM-based chips. My focus, in addition to my management role, was on UVM component and testbench development, regression test management (including maintaining and annotating the system testplan), and process automation via Perl scripts.During this time I gained extensive experience using Mentor Graphics tools, including QuestaSim (vlog, vsim, vcover) and Questa Verification IP (QVIP).

Santa Clara, Ca, Us

This was my first full-time job as a verification engineer. I was the technical lead charged with organizing the verification process for a large SOC. My work included writing verification tests, creating System Verilog testbenches, and developing a complete regression test strategy.One key element of the regression test flow was a tracking GUI I developed using Perl/Tk. This tool provided quick triage of results and tracked the debug effort of test failures.

Santa Clara, Ca, Us

In this role I applied my experience with FPGAs to the task of emulating SOC designs. I was responsible for targeting the SOC RTL to the FPGA, running place and route, closing timing, and debugging on the bench. I also designed and verified portions of the SOC logic. The design work was done in System Verilog, and the verification utilized System Verilog testbenches and was simulated using Synopsys VCS.

Design of electronic test equipment, including in-circuit testers and IC testers. This work included architecture and design of large PC boards, some of which contained over a dozen FPGAs. I was also responsible for making sure the designs passed all environmental, regulatory, and life tests.