Bob Silver Email & Phone Number

Benicia, Ca, Us

United States

Benicia, California

I provide free technical advice and support to seniors in my community that relate to PCs & their peripheral devices, networks & the internet, smart TVs & smartphones. This age group often lacks the knowledge to make proper use of current communication technologies. Helping them opens a new world of experience to them.

Roseville, California

With the move of computer manufacturing to Roseville, I assumed the responsibility for supporting the R&D Lab in their material procurement needs for prototype builds of new products. Staffing was increased from 3 to 17 people and in addition, the QA lab was retained.A collection process was setup in the factory for defective components which were analyzed in the QA lab. This helped determine the failure class of the components. Failure rates were monitored continuously and through feedback to suppliers these failure rates were driven down continuously allowing for less in-factory rework and field failures.A database was developed which allowed predictive modeling of new products.I took advantage of the 2002 Enhanced Early Retirement and retired in June 2002.

Cupertino, California

Responsibility for the technical portion of component/assembly sourcing in support of both NPI and current product computer system manufacturing. This included quality monitoring and evaluation of both current and potential new suppliers to the Computer systems Division.Developed a 3 sigma sampling process for incoming component inspection to minimize the need for 100% inspection of certain classes of electronic components.In addition, I managed the operation of the QA lab with the division.

Cupertino, California

Joined HP to transfer a semiconductor process being developed at the Palo Alto R&D wafer fab to a new fab being built in Cupertino.Once transferred, responsibility for process documentation, stabilization and continuous improvement as characterized by control charts and wafer yields.Interface with product, test and design engineering to drive continuous die yield improvement and device characterization.I assumed duplicate responsibility for the SOS wafer fab and held the dual positions until fab operations ceases in May 1985.In an attempt to forestall the fab closure,I proposed developing a standard product to “fill” the wafer fab and be sold by HP as a standard product. It was a logic array which could be programmed by the end user (FPLA) but the proposal was not adopted.

Sunnyvale, California

Maruman was a startup company. I had responsibility for:1. Capital equipment selection, procurement, installation and bring up.2. Staffing of the wafer fab with engineering and technician staff.3. Process development, production ramp up and ongoing quality controls.4. Interface with Marketing, product engineering and direct customers as required.Maruman achieved profitability 18 months after startup.

Cupertino, California

R&D position with responsibility to develop new process technologies, their stabilization, documentation and transfer to manufacturing.

Cupertino, California

Joined AMI as manufacturing engineering process manager. Responsibilities included process stabilization, controls, equipment maintenance and wafer sort die yields as well as staff supervision.This wafer fab manufactured the calculator chip for the HP 35 handheld calculator.

Princeton, New Jersey

Joined the team that invented the MOS transistor; I helped develop the first planar CMOS process and test chip vehicles for process characterization. This technology formed the basis for most electronic products in use today.I next worked on processes for producing ferroelectric memory devices in barium titanate single crystals.Following this, I developed the silicon storage tube which formed the basis of all airport x-ray surveillance systems.I next began working with ion implantation for modifying MOS devices characteristics. I developed a very early process simulator to predict device characteristics with implantation.I published several technical papers andReceived 7 US patents for my work. From May 1964 - May 1966 I was on military LOA serving on active duty in the U.S. Army.

Weapons Systems officerSupply officer

I had three coop work assignments. The first was in a system design lab in Poughkeepsie, working on some circuit board layouts for an enhancement to the IBM 360 computer.My second and third assignments were combined, working in IBM's Semiconductor Design and Processing Lab in Poughkeepsie. My project was to develop a two terminal current limiting device based on the tunnel diode. This work was submitted for my Master's thesis at MIT. Paul E. Gray was my thesis advisor.

Master Of Science (Ms), Electrical And Electronics Engineering

Bachelor Of Science (Bs), Electrical And Electronics Engineering

Activities and Societies: Eta Kappa Nu, Sigma Xi

High School Diploma, College/University Preparatory And Advanced High School/Secondary Diploma Program

Engineering Physics

Additional studies toward a Phd