Senior Process Engineer
CurrentKey Tasks:• Responsible for health and throughput of patterning on 1000s wafers/week. Coordinated dozens of new product integrations, including foundry products. Qualified process changes• Ensured devices were within spec by monitoring SPC trend charts, including 24/7 on call rotations• Worked with etch, thin films, polish modules to respond to out of spec trends. Worked with integration and yield teams to address defect trends• Setup experimental skews to support program deliverables • Collaborated closely with mask design teams to generate masks to meet program deliverables, including order of magnitude defect reductions and device performance improvements• Explored fundamental techniques to reduce device variability. Qualified more complex, integrated patterning changes to chip architecture • Established and coordinated collaborations among different engineering groups• Formed teams, coordinated material resources, and analyzed data in pursuit of novel projects such as identifying new materials for gate formation and exploring process flow simplificationsKey Accomplishments:• Trained and mentored seven engineers in both technical and cultural aspects of litho process engineer role• Generated nine published patents with three more pending publication • Developed technique to reduce variability of Extreme UV patterned lines, allowing 50% cost reduction at device patterning and earning two distinguished invention awards• Helped develop and qualify scheme to allow removal of Extreme UV litho layer from flow, reducing product costs by millions of dollars over program lifetime, and earning a divisional award