Bob Gardyne Email and Phone Number
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I am a Silicon Valley veteran with a career-long history of fixing staffing and technology roadblocks that prevent concepts from being realized into products that can be monetized. I have achieved my lifelong career goals of achieving commercial success in high performance digital and mixed signal printed circuit boards, chips (FPGAs, ASICs, SOCs), motherboards, add-in cards, consumer products, and systems from 1RU to three telco rack in size. I am also adept with enterprise-grade privacy and security, and software (firmware, platforms, websites, and mobile apps). I like to think of myself as a what a Renaissance engineer would be today, and I draw inspiration from Leonardo DaVinci. I am lucky. I got to design professional audio equipment and hear Tom Petty and Stevie Nicks at Berkeley’s Greek Theater on the Digidesign Venue system that I brought to market from certain architectural failure. I took over a busted MPEG2 Encoder ASIC project and finished with two chips that went to production on first silicon. I took a troubled MEMS-mirror optical switch prototype to a $3.25B acquisition by Nortel Networks. I am complete as a designer, a very lucky man, and yet I can’t help but want to do it again.I am at my best leading multi-disciplinary teams of ten to forty, where 35 years of management experience and broad technical background allow me to quickly focus on causes and determine and implement effective courses of action. My experience as Head of Product coupled with a lifetime of design engineering allows me to make excellent cost/quality/schedule tradeoffs and to know what to do to get the most out of each part of the product line.I am highly effective at staffing, project management, specification writing, presentations (created over 1,000 PPTX decks and 500 Excel models). I host cross-department/company meetings and webinars. I have a unique and successful methodology for hiring technical staff that I have developed from managing engineers and techs at eleven companies. I am surprisingly gregarious for an engineer, but then again, my mom was an English teacher, so its not a surprise that I write well. No ChatGPT ghostwriting for me, thank you, but I have engineered a two-level chatgpt4 prompt library to automate customer workflows.After a career in Silicon Valley and with both kids now out of our home, I am available immediately for new opportunities as a CTO, CIO, VP or Director Engineering for in-office/hybrid work relocatable outside of the Bay Area.
Rpg Associates
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Fractional And Full-Time: Head Of Engineering | Vp Engineering | Director Hardware Engineering | CtoRpg AssociatesOakland, Ca, Us
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Senior Director Engineering And Product DevelopmentBroadata Communications, Inc. Dec 2024 - PresentTorrance, Ca, UsDesign and develop AV communications products aimed at Class 1 medical and commercial markets -
Cto / Head Of Product/ Co-FounderOneva, Inc. Nov 2014 - May 2024CTO/Head of Product: UX, design,specification, development, test, debug, release and daily operations of mobile and back-end technology and staff for three-way trusted in-home and remote care on a enterprise-grade platform with provider and customer mobile applications. Security and privacy governance. Direct marketing, collateral design and production,COO: caregiver recruiting and training, client onboarding, customer service, daily operationsFounder responsibilities: Fundraising, pitch deck, partnership development, business models, and pricing analysis
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CtoSafetysitters, Inc. Jul 2014 - Nov 2014Design, development and operation of mobile and back-end technology and staff for premium and customizable mobile-oriented video-laden in-home care start-up.
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Vp EngineeringJupiter Systems Oct 2011 - Jul 2014Hayward, California, UsJupiter Systems is the leading worldwide supplier of display wall processors for command and control applications. At Jupiter, I'm responsible for engineering design, development, release and support of all systems, software, firmware, boards, FPGAs, mechanical, test & regulatory. Drove Jupiter’s next gen PCIeGen3/GPU architecture and implementation. Drove development & release of Canvas - enterprise client-server collaboration application for Display Wall Processor, PC clients and mobile (IOS/Android) – H.264 multicast, HLS streaming, WPF annotate, chat & invites, role/object-based security. HDCP system architect. -
Vice President EngineeringRgb Spectrum Mar 2007 - Aug 2011Alameda, California, UsCreated hockey stick growth to 2x revenue from 2007-2011 with refresh and expansion of established product lines and creation of two new product families (Switcher & Control Applications).Responsible for all software, firmware, boards, FPGAs, mechanical, test & regulatory for video product line including client-server control room application software, HDMI/HDCP compliant video wall processors and multi-format digital video switchers, and compression/recording/streaming devices.Personally drove hiring of 29 over 4 years to double engineering staff; created Test, GUI, and Engineering Services groups; tripled FW staff. Created highly loyal team. -
Director Of Hardware EngineeringDigidesign Apr 2002 - Mar 2007Burlington, Ma, UsDirector w/ one manager, staff of 18, responsible for hardware specification, design, verification, and regulatory & environmental certification for professional and consumer audio products including PCBAs, FPGAs, firmware & cables. Hardware Team Lead for Venue Livesound/Concert product (project manager for last year of development and through NPI).• Drove Digidesign from $80M revenue to $200M by shipping 11 major consumer & studio products in five years with focus on NPI, time-to-market, COGS, and design for offshore mfg to achieve consistent 50-60% gross margins.• Saved a failing Digidesign Venue project targeted at new Livesound concert business segment. Turnaround resulted in market dominance displacing arch-competitor Yamaha, and generating $15M in the first two years, now over $30M/yr. -
Director Of Hardware EngineeringDigidesign 2002 - 2007Burlington, Ma, Us -
Director Of Hardware EngineeringNortel Networks May 2000 - Apr 2002CaNortel Networks acquired Xros for $3.25B in May 2000.Director w/ two manager, staff of 17, responsible for digital & mixed (analog+highV) PCBAs, firmware, opto-electronic modules, FPGAs, backplanes, PSUs & cables for 1152 x 1152 MEMS-based redundant optical cross-connect switch.Managed fabrication and verification of five 288 port pre-production qualification units. -
Director Of Hardware EngineeringXros Nov 1999 - May 2000Director w/ one manager, staff of 15, responsible for digital & mixed (analog+highV) PCBAs, firmware, opto-electronic modules, FPGAs, backplanes, PSUs & cables for 1152 x 1152 MEMS-based redundant optical cross-connect switch.Drove project from working benchtop 4-channel prototype to fully configured three rack redundant system. Redundant cPCI PowerPC control plane. Dynamically unstable MEMS-driven mirrors w/ 300V drive and co-located mirror position sensors w/ full-scale 10 mV outputs. A rocket science project targeted to have telco reliability and 40 Gbps fiber traffic.Xros was acquired by Nortel in May, 2000.
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Director Of System Engineering & VerificationStellar Semiconductor Jun 1998 - Nov 1999Gurgaon, Haryana, InManaged staff of three test and verification engineers responsible for 3D graphics core module and chip-level verification, packaging selection, and reference and engineering evaluation board design.Taped out and delivered a 400K gate 0.35u standard cell 3D graphics core to a set top box ASIC supplier.Created statement of work and schedule for 1.5M gate standard cell gaming project.Stellar Semiconductor was acquired by Broadcom in November 1999. -
Director Of Hardware EngineeringSilicon Vision Jun 1996 - May 1998Managed group of four including three principal/staff engineers (Analog, ASIC/FPGA, Layout/Mechanical) responsible for all hardware & mechanical design of PC desktop and laptop cameras including ASIC, PCB, optics, plastic enclosure, cables & connectors.Conceived, developed and shipped laptop digital video camera with novel EMI shielding ferrule/camera connector.
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Asic Design ManagerLsi Logic Mar 1994 - Jun 1996San Jose, Ca, UsManaged MPEG Source Encoder Group of Consumer Product Division with staff of eight ASIC design and verification engineers.Responsible for architecture, design, tape-out & embedded FW of HD-scalable MPEG-2 Encoder chipset: 110K gate & 250K gate ASICs w/ embedded RISC uPs and micro-coded functional units in 0.5u embedded array. Both ASICs fully functional in one revision: 720x576 & 25 fps. Evaluated, specified & ordered workstations & EDA tools for 35 person division. -
Asic Design EngineerHeadland Technology Jul 1992 - Mar 1994Debugged video ASIC memory access failure by writing new simulations and comparing results with as-built observations.Designed modules for two video graphics ASICs (0.9u and 0.7u)– shipped 1M units. Took over failing BIT-BLT module to completion. Transitioned with design team from LSI Logic schematic tools to VHDL. Wrote and administered VHDL exercises for group interviews.Acquired by LSI Logic March 1994.
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Manager Of Hardware EngineeringVideo Seven Mar 1990 - Jun 1992Managed staff of six (three Digital Engineers, one Analog Engineer, one Mfg Engineer, and one technician) responsible for design of production VGA boards for retail and OEM customers including HP, Siemens, Unisys, Zenith & Sun.VGA 1024i and VRAM II won PC Magazine awards.Merged w/ G2 to form Headland Technology.
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Hardware Staff EngineerVideo Seven Aug 1988 - Mar 1990Designed special projects for Sun & Tektronix using Video7 chipsets and PLDs. Sun project (386i) provided up to four VGA windows via a framegrabber and DMA engine to the Sun bus. The Tektronix project used a triple rate 180Hz output with sequential red, green blue fields to drive a monochromatic one pel/pixel display with LCD color shutters.Video Seven merged with G2 to form Headland in March 1990.
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Firmware Design EngineerNorth Star Computers Feb 1985 - Aug 1988Firmware design for multi-user business computers, including EGA and VGA BIOS development, inter-processor hardware and software communications interface, protected mode BIOS development. Novelle Netware port including print spooler and hard/floppy disk drivers.
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Data Network Design EngineerBank Of America 1982 - 1985Charlotte, Nc, Us
Bob Gardyne Skills
Bob Gardyne Education Details
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University Of California, BerkeleyComputer Architecture & Digital Design
Frequently Asked Questions about Bob Gardyne
What company does Bob Gardyne work for?
Bob Gardyne works for Rpg Associates
What is Bob Gardyne's role at the current company?
Bob Gardyne's current role is Fractional and Full-Time: Head of Engineering | VP Engineering | Director Hardware Engineering | CTO.
What is Bob Gardyne's email address?
Bob Gardyne's email address is rg****@****ail.com
What is Bob Gardyne's direct phone number?
Bob Gardyne's direct phone number is (800) 971*****
What schools did Bob Gardyne attend?
Bob Gardyne attended University Of California, Berkeley.
What skills is Bob Gardyne known for?
Bob Gardyne has skills like Embedded Systems, Fpga, High Speed Digital, Firmware, Asic, Pcb Design, Hardware Architecture, Systems Engineering, Semiconductors, Device Drivers, Hardware, Vhdl.
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