Bob Ledoux Email and Phone Number

• Lead Architect and Senior Hardware designer on ATCA Blade products (Cavium Based Packet Processor and Fulcrum based 40G Switch Fabric.• Responsible for developing project requirements, schedules, cost estimates, man-power forecast, as well as define the product concept.• Design expertise in high speed circuit board design and layout, signal integrity, power distribution, thermal analysis and management, system integration and test.• Designed the payload FPGAs on the GE ATCA Blade… Show more • Lead Architect and Senior Hardware designer on ATCA Blade products (Cavium Based Packet Processor and Fulcrum based 40G Switch Fabric.• Responsible for developing project requirements, schedules, cost estimates, man-power forecast, as well as define the product concept.• Design expertise in high speed circuit board design and layout, signal integrity, power distribution, thermal analysis and management, system integration and test.• Designed the payload FPGAs on the GE ATCA Blade products. Integrating a number of control plane functions into the FPGAs.• Designed Cavium packet processor modules in the PCI-X/PCIe form factor. Show less

Designed a number of complex FPGA’s for SBS. • Designed an FPGA that implemented the I-TDM protocol standard (SFP.0/1). I-TDM is a multiplexed voice over packet protocol that is optimized for Voice LANs and Packet Backplanes. The FPGA also includes the following functions: An 8-stream MVIP interface, a 512 channel TSI, dual GbE MAC/PCS cores, various integrated descriptor and Jitter Buffer memories, a 32-bit NIOS-II processor, a DDR and SDR SDRAM controllers.• Designed an ATM cell… Show more Designed a number of complex FPGA’s for SBS. • Designed an FPGA that implemented the I-TDM protocol standard (SFP.0/1). I-TDM is a multiplexed voice over packet protocol that is optimized for Voice LANs and Packet Backplanes. The FPGA also includes the following functions: An 8-stream MVIP interface, a 512 channel TSI, dual GbE MAC/PCS cores, various integrated descriptor and Jitter Buffer memories, a 32-bit NIOS-II processor, a DDR and SDR SDRAM controllers.• Designed an ATM cell auto-discovery and time-stamping function. The FPGA provided UTOPIA II interfaces, a CAM device controller, VPI/VCI re-mapper, time-stamp function, and CRC-32 generator/checker function. • Designed a 1024-channel HDLC controller to POS FPGA. The FPGA provides 8-HMVIP streams to support 32-E1 ports. Each HDLC Channel can support fractional DS0’s. The FPGA supports CCITT-16, CRC-16, and CRC-32. Captured HDLC frames are MPLS tagged and forwarded to a POS interface. The FPGA also provides various OAM statistics, a PPC interface. Also design the following boards:• Designed a PICMG AMC.1 form-factor I/O module to provide an OC3 to PCI-Express SAR function.• Designed a PICMG AMC.1 form-factor I/O module to provide a T1/E1 to GbE inter-working function.* A 6U CPCI 2.16 compliant, 32-Port T1/E1/J1 Monitor card. The blade includes T1/E1 Framers, a 1024-HDLC channel to POS FPGA, WINTEGRA 737 Packet Processor, IPMI function, 2.16 Ethernet, PPMC site. Show less

Designed a 16 channel HDLC Controller FPGA.

• Designed a 4-channel 80MHz ADC acquisition PCI module.• Designed a data-acquisition controller FPGA that provided all the control, triggering, time-stamping and programmable buffering for high-speed ADC & DAC boards.

Board Designs:• Contact Image Sensor (CIS) image reader/frame grabber module.• Motorola processor based modules.• Motorola 68HCF11 micro-controller based Smart Card and mag-stripe controller module.ASIC Design:• Designed a 20K gate 0.85u AMI standard cell gate array. The design consolidated the following functions: Keyboard controller, LCD video controller, sound generator, ADPCM, UARTs, SPI interface, Memory arbiters, and DMA controllers.

XILINX design consultant for a microphone array research project.• Microphone Array Processor controller. The controller provided high speed DMA capability between a VIC/VAC interface, a MC68332 processor and eight AD21020 DSP modules.