Bob Macdonald Email & Phone Number

Arlington, Va, Us

Active secret security clearance

Principal member of the FPGA design team that is responsible for all aspects of the design, functional verification, and lab debug of the next generation Software Defined Radio (SDR) for communications satellites. This product utilizes the following technologies: 10 Gigabit Ethernet MAC and PCS/PMA in 10GBASE-R mode, Fibre Channel, Aurora Bus, and Ethernet/IP/UDP/ARP protocols. My specific tasks involve the Xilinx KINTEX-7 FPGA as follows: • Successfully designed, verified with ModelSim, and lab tested the 10GE UDP/IP hardware protocol stack, which is used to encapsulate/de-encapsulate IP/UDP packets from an Ethernet frame. This module also implements the IP Address Resolution Protocol (ARP).• Integrated Xilinx 10GE Subsystem with UDP/IP hardware protocol stack.• Used Xilinx Vivado tools workflow to develop the KINTEX-7 FPGA.• Created ModelSim verification testbench to perform block level and system level functional testing.• Assisted with lab debug of another engineer’s design. Found problems and created verification test bench to verify design code fixes.• Wrote detailed functional specification for my design.

Us

Senior member of the FPGA design team that is responsible for all aspects of the design, functional verification, and lab debug of the video controller for the Pixtronix PerfectLight Display, which features less power consumption than LCD displays. This display utilizes the following technologies: MEMS pixel light modulator (Digital Micro Shutter (DMS)) and Field Sequential Color (FSC) algorithms. My specific tasks involve the Xilinx FPGA’s as follows: • Successfully designed, verified, and lab tested the Power Management Unit FPGA and board for the DMS video controller.• Provided support for DMS video controller. This includes design, hardware specification, verification testbench creation and simulation, Xilinx design flow (synthesis, mapping, place & route, and programming file generation), and lab debug with Xilinx ChipScope Pro Analyzer. Also provided support all the internal groups.• Created power-up/power-down system scripts and verified correct operation of the output power supplies.• Responsible for the functional verification of the next generation color pipe for the DMS video controller. This includes creating the testbench and writing all the various tests.• Used MATLAB, ModelSim, Xilinx Vivado, ISE Design Suite and ChipScope Pro Analyzer.

Chicago, Illinois, Us

Senior member of the FPGA design team that is responsible for all aspects of the design and functional verification of the BSR 64000 DOCSIS 3.0 CMTS Edge Router. My specific tasks involved the TX32 Decoupled Downstream Module as follows: • Modified the TX32 FPGA VERA verification environment to provide IPv6 support.• Wrote tests that successfully verified the new TX32 QOS scheduling features. These features include: per channel/queue rate limit, per channel/queue class based priority, and per queue max credits maximum burst.• Assisted in the effort to convert existing VERA testbench to SystemVerilog.

Member of the FPGA design team that is responsible for all aspects of the design and functional verification of the TDM-to-Ethernet Protocol Translator. The Altera Stratix FPGA is designed to translate ATM AAL5 packet data over T1/E1/J1 links into Ethernet frames.

Sunnyvale, California, Us

Application Engineer responsible for providing customers technical support for all the DesignWare IP, both digital controllers and mixed-signal PHY’s.

Member of the ASIC design team that was responsible for all aspects of the architecture, design, and debug of the high speed switch fabric ASIC for the next generation Avici Core Router. The link data rate of the new ASIC is 2.4Gbps and the system is capable of supporting a dual OC192 card at full line rate.

Member of the design/DV team that was responsible for all aspects of the design and functional verification of 10Gbit Ethernet System on a chip (SOC). The system consisted of the following: 10Gbit Ethernet MAC, Physical Coding Sublayer (PCS), WAN Interface Sublayer (WIS), XGMII Extender Sublayer (XGXS), and a SPI-4.2 system interface. The Specman e test environment included Specman's advanced e Reuse Methodology (eRM). Responsible for both the Verilog design and functional verification of the 10Gbit Ethernet MAC module.

Developed system architecture for Enterprise Giga Switch Router. This stackable product can support 80 Gigabit Ethernet ports at full duplex line rate. Policy based filtering and forwarding can be done at the Layer 2 or Layer 3 level with data flow forwarding and management for Layer 4 packets.