Bob Waller Email & Phone Number

Holly Springs, Nc, Us

Retired Marvell Technology

Santa Clara, Ca, Us

Building and troubleshooting RAID servers and hardrives for Cloud computing.

Santa Clara, Ca, Us

Support ASIC designs , test, and manufacturing for a world leading semiconductor company - Global Foundries.http://www.asicnorth.com/http://www.globalfoundries.com/

Provide desktop support for EPA employee's and validate new refresh computers.

Hanover, Md, Us

Provide Technical and Application support for Electronic Health Records application ( EPIC ).

Austin, Texas, Us

Write system verilog testcases to achieve functional coverage and enhance Uvm testbench for ethernet phy soc asic.

Currently developing VIP for DFT verification of an 1149.1 Compliant TAP controller. Starting from the ground up using UVM/SV to build the interface UFC env, agents,scoreboard,sequencers,drivers, monitors.

Actively researching new opportunities in the Semiconductor Industry for DFT, ASIC Verification, and VLSI Test engineering services on products ranging from embedded CPU's, ASIC Array BIST engines and memory IP to Digital IC's and Complex SOC designs. Familiar with metric driven verification using System Verilog in the UVM environment, Test pattern generation using Cadence Encounter Test for ATPG, ABIST, ASST, I/O, and Teradyne Ultraflex test program and pattern development.

Specialized in Array Built-In Self-Test design and verification using Verilog HDL, System Verilog, and Cadence Incisive e Manager. Enhance verification test bench to include a pattern checker for a complex DRAM BIST engine, mapped ABIST designs from 45nm to 32nm technology. Comply with IBM 32nm ASIC methodology requirements to release ABIST core engine from design to silicon with first time success. Implement DFT strategies using Cadence Encounter test for a multi-processor networking chip with emphasis on ATPG, Test coverage,MFG pattern support and delivery. Travel to manufacturing test facility to work with test and production engineers to support first wafer and module test bring up using Teradyne Uflex ATE.

Characterization team lead for the Microsoft XBOX 360 microprocessor chip. Work directly with manufacturing and product engineering teams to bring-up first silicon for wafer and module. Debug test vectors using ATE Teradyne Uflex. Enhance characterization and mfg test program specifications, First time success and on time delivery to Microsoft for Christmas 2005 Introduction. Provide test engineering skills to characterize power and performance of IBM's embedded Power PC designs. Work closely with logic and circuit designers to debug hardware test issues.

Convert functional simulation for critical path's and implement architectural verification and performance testing for Power PC low power embedded microprocessor SOC's. Working closely with design and circuit teams to provide high quality test programs to support manufacturing and process engineering teams.

During this time span did various jobs starting with maintenance of VLSI Memory testers, support manufacturing operations , and developing test programs for IBM semiconductor chips.- manufacturing test technician for IBM's Blue Lightning 32 bit micro-processor chip- test program development and characterization of IBM RS6000 workstation chip set.- test program development and manufacturing support for IBM's Token Ring chip.