Bohan Zhai Email & Phone Number

新加坡

• Design:
• Design and simulate multiple digital IPs (RTL) based on 12nm and 28nm process libraries, including RISC-Vbased CGRA PE arrays for accelerated computing (ASIC design), Integrate these IPs into the SoC platformand.
• Energy Efficiency Improvement: Perform block-level optimization using advanced digital flow andtechniques such as DVFS to reduce area, dynamic/leakage power while maintaining reasonable speedperformance using ASIC.
• Cooperate with others for tape-out.Chip testing and data analysis:
• Prepare test plan, test automation and PCB design for bench-top testing of existing ASIC chip.
• Based on C and Python, develop software and test script to test the actual performance of existing chips suchas cryogenic RISC-V and RISC-V+CGRA accelerators.

中国 四川省 成都市

• Responsible for the construction and optimization of 3A algorithm: An automatic white balance algorithm(AWB) module including grayscale world was built based on C++ language; Evaluate the accuracy andperformance of.
• Automatic configuration of Json files required for 3A algorithm based on C++.

Master'S Degree, Integrated Circuit Design

Core curriculum: Digital IC Design, SOC Design, Digital Signal Process, DFT, Analog IC Design

Master'S Degree, Integrated Circuit Design

Core curriculum: Digital IC Design, SOC Design, Digital Signal Process, DFT, Analog IC Design

Bachelor Of Engineering - Be, Eee