Amarender Boreddy work email
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Amarender Boreddy personal email
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Worked in different phases of Front-end VLSI flow in different organizations. Having around 15 years of industrial experience in networking and dsp chip designs.Specialties: Expertise in design/RTL coding & micro architecture definitions.AXI Bridge design, Fabric interface design.RDMA protocols processing, DMA Engine, Segmentation module designs, T10-DIF support for storage protocols, Multiple protocol switching design Layer 2-3 switching & classification Hands on experience on buffer schemes, Control Caches, queue setups, classification and packet filters and parser logic.DSP designs, NPML filter design, Calibration & Interpolator designs
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Asic Design EngineerApple Oct 2022 - PresentCupertino, California, Us -
InvestorSimbo.Ai Aug 2017 - PresentCambridge, Massachusetts, Us -
Senior Staff Design Engineer (Smts)Amd Dec 2018 - Sep 2022Santa Clara, California, UsData Center group -
Soc ArchitectChelsio Communications Apr 2016 - Dec 2018Sunnyvale, California, UsASIC architect for unified wire offload project, NVMe over RDMA & iSCSI -
Member Of Technical StaffChelsio Communications Oct 2008 - Mar 2016Sunnyvale, California, UsASIC development(Networking) experience.• High-level architecture exploration, micro-architecture development of complex blocks of highfrequency and multi-million gates in advanced process nodes.• Design, RTL coding, synthesis, static timing analysis, gate-level simulations, DFT, lint, formal-verificationRDMA protocols processing, Segmentation module designs, T10-DIF support for storage protocols, Mutliple protocol switching design Layer 2-3 switching, classification,Buffer design for protocol switch & error handling -
Sr Design & Verificaiton EngineerTime To Market Inc (Cyient) May 2007 - Oct 2008-Micro architecture, IP integration, RTL design for Digital Imaging Processor for camera applications-Dark Signal Non Uniformity Interpolator module, DMA & SPI module designs
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Lead Design EngineerConexant Systems Feb 2006 - May 2007Irvine, Ca, UsResponsible for implementation activities for conexant core groups. Worked on different projects to handle Synthesis, (pre & post layout)STA, DFT, MBIST & Formality(LEC) -
Senior Design EngineerAgere Systems Feb 2002 - Feb 2006San Jose, Ca, Us- Work on storage solutions(viterbi detector & dsp related design works) and had worked on block level design(RTL coding) synthesis, sta & formal, architectural verification, GLS and SOC verification. Had good work experience in Low power methodology applied/tried on the existing design to get low power solutions.- Designed Viterbi detector, Co-efficient calibration module & NPML Filter module
Amarender Boreddy Skills
Amarender Boreddy Education Details
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Indian Institute Of Technology, DelhiVlsi Design Tools & Technology -
Chaitanya Bharathi Institute Of Technology (Osmania University)Electronics & Communciations
Frequently Asked Questions about Amarender Boreddy
What company does Amarender Boreddy work for?
Amarender Boreddy works for Apple
What is Amarender Boreddy's role at the current company?
Amarender Boreddy's current role is ASIC Design Engineer at Apple.
What is Amarender Boreddy's email address?
Amarender Boreddy's email address is am****@****inx.com
What schools did Amarender Boreddy attend?
Amarender Boreddy attended Indian Institute Of Technology, Delhi, Chaitanya Bharathi Institute Of Technology (Osmania University).
What are some of Amarender Boreddy's interests?
Amarender Boreddy has interest in Children, Economic Empowerment, Education, Environment, Science And Technology, Arts And Culture.
What skills is Amarender Boreddy known for?
Amarender Boreddy has skills like Asic, Vlsi, Soc, Verilog, Rtl Design, Rtl Coding, Debugging, Logic Synthesis, Dft, Digital Signal Processors, Low Power Design, Ic.
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