Brajesh P. Email and Phone Number

I contributed in successful design, development and implementation of IITB-NavIC-SOC. The chip is tested and found to be functional for its intended uses. My contribution include, establishment of complete ( frontend and backend ) SoC flow using Synopsys environment for IITB-NavIC-SOC. It ’s NDM creation, netlist-to-GDSII generation, signoff, post-signoff activities, bond-diagram creation and test-board design, development, debug and testing. This chip comprises of 1M gates which houses AJIT microprocessor , RF resampler correlator and memory. This project was sponsored by MeitY, GoI.My other deliverables include, Silicon proven Analog and Mixed Signal systems and components viz. IEEE FireWire, PLL, BGR, LVDS comparators etc. These products were sold to multiple customers as Silicon proven IPs.In addition, using Silicon data, I have worked on novel planar CMOS technology compatible power MOSFET devices design, modeling and its characterisation.