Brandon Fry Email & Phone Number

Santa Clara, Ca, Us

Redmond, Washington, Us

Working on designing FPGA based ML accelerators for Azure

Charlotte, North Carolina, Us

• Responsible for implementing next generation F-35 Helmet Mounted Display Tester (HMDT). This required full redesign of the FPGA to accelerate the video distortion algorithms responsible for aligning flight symbology with pilots eyes, and result in a 30x improvement to video refresh rate over the previous generation. This required the following tasks to be accomplished: ○ Design and simulate via Matlab a 3rd and 5th order polynomial distortion algorithm to manipulate 1280 X 1024 pixel video at a rate of 30Hz. ○ Pipelined implementation of the distortion engine in VHDL to utilize the minimal number of DSP multipliers and block ram while still meeting the refresh rate requirement. ○ DRAM interface and arbitration logic to buffer incoming and outgoing video data and provide flow control to the DVI input and outputs, as well as internal distortion engine interfaces.○ FLASH interface and Run Length Decoder module to store and minimize the space required for test images.○ RS485 interface and custom protocol for updating distortion coefficients in real time.○ Defined proprietary data format to support full range and resolution for distortion coefficient values.○ Utilized Xilinx timing and synthesis tools to generate functional FPGA image for release.• Reduced the HMDT programs utilized hours and resources by modifying existing hardware to support next generation requirements.• Met all customer and company milestones resulting in full payment for HMDT program.Developed initial board level test procedures for commercial Head-Up Display (HUD) hardware.

Beaverton, Or, Us

• Architected and implemented the FPGA system which acted as the waveform processor and primary datapath in the AWG5200. The system was responsible for reading waveform from memory, handling different sequencer events, and driving it to the DAC without glitching the output. This required the design and implementation of:○ Custom 12.5 Gbps JESD204B compliant interface to drive data to the digital-to-analog converter.○ Custom 12.5 Gbps, 8b10b bus used to transfer waveform data and sequencer commands.○ DDR3 controller utilizing the Altera DDR3 controller PHY IP with ping-pong and fly-by topology.○ Waveform processor responsible for remapping the data to achieve different interpolation rates and waveform granularity of 1.○ Custom parallel bus used for realtime control of the waveform processor from the sequencer machine.○ Waveform expansion logic to throttle the system and imitate slower sampling rates.○ Pipelined design to ease on timing closure and allow for increased data throughput.○ Crossings across multiple clock domains• Utilized Altera TimeQuest for meeting FPGA timing closure.• Wrote a wide array of system driver code in C++, which included control code, diagnostics and system calibrations.• Developed scripts in C++ and C# for debugging FPGA and system functions• Designed and implemented custom DAC synchronization algorithm of which patent application was filed.• Worked on bringing up new boards and debugging analog and RF circuitry.• Led team of 4 engineers to produce functional proof of concept of potential future product; Architected the system and generated project requirements, managed schedule and resources, gathered VOC and completed proof of concept within desired time frame.

Corvallis, Or, Us

• Teachers aid for ECE 111 (Intro to electronics).• Teachers aid for ECE 112 (Intro to electronics II).• Teachers aid for ECE 272 (Digital Logic Design).• Teachers aid for ENGR 201 (Electrical Fundamentals I).• Provided extra instruction on class material in group recitation.• Graded students lab and recitation assignments and provided feedback on missed problems. • Generated lesson plan on digital adders for ECE 272 and conducted lecture when professor was absent.

Rueil Malmaison, Paris, Fr

● Developed Advanced Service Terminal in C# which allowed technicians to manipulate and visualize the performance of the power correction units in the field.● Designed and implemented C# Modbus scope to measure units output signal via an ADC and display it in the Advanced Service Terminal.● Performed testing on different units to ensure new software releases worked as expected and units met power factor correction requirements.

Berlin, De

• Reduced duration and improved reliability of pacemaker testing by contributing to C# library of automated tests.• Developed C firmware which was loaded onto pacemaker to control different functions used during automated tests.• Wrote test procedures for all newly developed automated tests, and held team reviews to ensure that all requirements and standards were met.

• Redesigned PCB for FM receiver used in ECE 473 to professors specifications.• Began design and construction for telepresence robot project.• Developed demos for students displaying the different concepts to be learned in the courses.• Researched benefits chameleon board provided to ECE 272.

• Developed software and database system in C# and which integrated into current factory edge databases to track, disposition, and adjust inventory for nonconforming material.• Performed failure analysis on GE modules and compiled finding into document which was sent to vendor.• Created beam profiler correlation process and provided data used to improve 3rd party measuring devices.• Researched interconnect solutions for Teleos module which met size and current requirements.• Provided support for production staff by assembling modules.

Master Of Science - Ms, Data Science

Bachelor Of Science (Bs), Electrical And Electronics Engineering

Minor, Computer Science

Hardware Dsp: A Guide To Building Dsp Circuits In Fpgas

Dsp: Understanding Digital Signal Processing

Verilog/System Verilog For Design And Synthesis