• Project Lead / Project Management of 40nm AI R&D chip design with digital synthesis and place and route tools • Project Lead / Project Management of 14nm finFET SOI eDRAM, SRAM & EFUSE technology qualification vehicles • Creation of a scan chain system to test and debug SRAM, eDRAM and EFUSE technology qualification vehicles• Creation of a Verilog simulation, verification and test environment for the 14nm embedded eDRAM• Spectre XPS extracted simulation and verification of the full chip 14nm eDRAM testsite• 14nm Layout of eDRAM sub cells in cadence tools and DOE experiments in caliber tools• Fet level design, Verilog, Spectre and Ultrasim simulation and verification of a 14nm PCM memory testsite for IBM.• Synthesis and place and route on all digital blocks for a PCM memory chip and an artificial intelligence R&D chip design in a 50 nm technology node• Rebuilding of an archived full chip Verilog environment for a flash memory chip• Sense amplifier design and verification for a PCM memory chip in a 50 nm technology node• Full chip extraction and analog simulation verification in a 50 nm technology node

Treasurer and Board Member of The Epilepsy Foundation of Vermont2014 ­- 2017 Volunteer Experience • Responsible for dispensing large operational payments and budget planning. • Responsible for finding, writing, submitting and carrying out grant proposals and their associated projects. Most recently the "Emfit night time motion sensor for Vermonters" project. • Co-creator of an android mobile phone application that "sensed" seizures and called others for help when the phone was worn by users with a jogging strap. Written in Java. • Volunteered at events throughout Vermont such as Casino Night, Fair Raffle, Walk for Epilepsy, Mud Volleyball, The Big Chill and THEM Live at the Eagles Club. • Created promotional videos for TV and Web, and audio spots for radio • Made numerous TV and Radio appearances for the Foundation. • Volunteer of the year 2014 and 2016 • Keynote speaker at annual meeting 2014

2006 ­-- 2018 Experience • LPDDR4 / LPDDR4X input buffer circuit designs at 4266 Mbps in Nanya's 20nm technology node. • OCD and ODT impedance calibration circuit in Nanya's 20nm technology node. • LPDDR3 input buffer design at 2133 Mbps in Nanya's 30nm technology node. • PLL feasibility investigation for DDR3 in Nanya's 30nm Technology node. • Chip lead on the porting of a LPDDR3 design into Nanya's 30nm technology node. • Full chip simulation and verification of a LPDDR3 design in Nanya's 30nm technology node. • Nanya IO Expert Panel: led a multi-site team in the creation of a "how to" document for I/O circuit design and verification on future Nanya chip designs • LVS and DRC layout design and repair in Micron's design environment at the 50nm node. • LVS and DRC layout design and repair in Microns design environment at the 68nm node. • Design and verification of a SDR and DDR combination I/O circuit in the Micron design environment at 68nm technology node. Noise, power bus, and package analysis were required to verify that the design met the specification and frequency targets. • DDR3 DRAM Datapath circuit design in Qimonda design environment at the 70nm technology node. • Full chip simulation and verification of DDR3 DRAM specifications with nanosim and verilog. • Creation of the Datapath education module for the Burlington Design Center. • Nanya representative to the JEDEC Technology Group.

· Responsible for IO design sizing, scheduling and resource management of the ASIC IO design team. Approximately 25 to 30 team members on two sites and multiple off site contractors. Represented the Asic IO team on technical issues with Customers. · Electrical Design of Input/Output circuits to be used by IBM ASICS customers on various applications. The IO's designed were AGP2X, AGP4X, AGP8X, RAPIDIO, PCI, PCIX, PCIXDDR, LVDS, LVTTL, CMOS; HSTL and combinations which met multiple specifications on one IO PAD. Many designs required the use of impedance compensation to meet industry standard specs. Each electrical design included generation of test, wiring, noise, EM, and current specifications as well as datasheets, and delay rule generation. · New Delay Rule (NDR) Generation ­ Responsible for generating Delay Rules for entire libraries of IO's and internal circuits. Led a small team of programmers and engineers in the development of a new GUI driven NDR generation tool that interfaces with cadence schematics and creates a more intuitive data generation process. · Model to hardware and technology qualification ­ Performed model to hardware analysis on IO's for qualification of IBM's technologies including ASX analysis of IO ring oscillators, driver IV curves, receiver switch points, AC path, and short circuit analysis. · Acted as a liaison for designs coming into the IBM ASIC library from outside sources. This role required me to get involved in IBM's DASL and USB IO designs. · Department canvasser for the Employee Charitable Contribution Campaign