Test ecosystem development

Modus ATPG, Diagnostics, and Data

SLM Data Acquisition ( ALE ) *ATE Interfaces & Data Integrity HSIO Structural High-speed testing *Primary architect for structural test using PCIE/USB/1149.10 etc..Cell-Aware and Advanced Process Node Test * Flow Architecture & Design - Defect Modeling: SPICE, Waveform Behavioral Identification - Physical Diagnostics Modeling and Physical Extraction - Emphasis on SOI, FinFET at Low Geometries * ATPG TetraMAX Diagnostics * Physical Diagnostics Architect - Physical Based Defect Analysis (Routing and Cell Layer) * Volume and single part analysis Customer SupportR&D Support

DFT Insertion/Verification * Full Scan * Compression Scan * Stuck-At,Transition (@speed) Scan * MBIST * JTAG TAP * Boundary Scan * Simulation * Post-Silicon Debug DFT group team lead providing implementation, verification, and support for an ASIC design services provider. Worked closely with front end, physical design, and ATE engineers to provide DFT services from RTL to post-silicon testing. Specialties: DFT, ASIC, MBIST, Scan, BScan, Perl, TCL, Cadence RC, Syntest, Encounter Test, NCVerilog