Brian Grace Email & Phone Number

Burlington, VT, US

Williston, Vermont, United States

Lead a successful FEOL tape-out for a fully custom LPDDR4 DRAM chip. Directly responsible for a group of twelve physical design engineers, the quality of the physical design of multiple products, plus my own engineering work. Layout design of analog, custom digital, and standard cells. I am also responsible for hiring and recruiting applicants.

Williston, Vermont, United States

Successfully taped-out three different DRAM products. I lead 8 revisions of 2 different chips during this time. I had experience working on four different products simultaneously. Experience in DDR4 and LPDDR4. I designed many analog and digital layout circuits and worked on chip level floor planning. Experience with standard cell design. Fluent in.

Assisting Dr. Eva Cosoroaba in EE 082 Linear Circuits II Laboratory.

Burlington, Vermont, United States

Assisted Dr. James Kay in EE100 Laboratory. Assisted students with lab procedures, troubleshoot lab equipment, and graded lab reports.

Assisting Dr. Paul Hines in Electrical Engineering 100.

Arlington, Vermont

Bennington, Vermont

A summer internship that I acquired after my senior year of high school. I learned basic wiring, how to read schematic diagrams, and edited AutoCAD drawings.