Brian Magnuson Email & Phone Number

Seattle, WA, US

Espoo, Southern Finland, FI

• Simultaneously integrated Eta technology into two product lines. First through an FPGA into anexisting platform and also embedding the IP in an upcoming ASIC.
• Developed an additional FPGA to assist in system integration of the ASIC project with the analogportions of Eta technology due to IO constraints.
• Managed internal outsourcing of the verification of that device due to local staffing shortfalls.
• Directed the local end of ongoing integration of the former Eta office with Nokia corporate including IT and building services.

Cambridge, MA, US

• Early employee of start-up focusing on dramatic improvements to the power efficiency of RF power amplifiers.
• Lead designer for implementing all digital functions including: - Digital predistortion (DPD) and other DSP functions. - JESD204B interface to DACs/ADCs. - Integration with embedded CPUs including ARM and MIPS.
• Developed successive generations of FPGA based demonstration platforms to feature various aspectsof the technology to customers and enable further development.
• Taped out a 28nm ASIC of the same technology suitable for integration in a full radio.
• Managed all internal CAD/IT resources and contracts with telecom, cloud computing, and CAD vendors.
• Participated in a successful exit with the acquisition of Eta Devices by Nokia.

Palo Alto, California, US

• Designed and implemented 1GHz 128-way Network Processor handling traffic at 100Gb/s, full-duplex.
• Custom instruction set with full set of bit manipulation and header processing instructions.
• Interfaces to a multi-port on-chip 128Gb SRAM and an array of accelerator functions.
• Personally managed the core processor module through place and route to timing closure.
• Designed all the digital logic for a 3-port FCoE switch excepting the MACs.
• Built complete verification infrastructure for the egress path of a switch fabric device.

Santa Clara, California, US

• Performed functional verification for full custom x86 macros.
• Wrote and executed a test-plan for an x86 microcode engine.

Round Rock, Texas, US

• Designed and verified peripherals and support logic for an ARM CPU embedded within a networkattached memory controller including: - A producer/consumer model messaging engine to interface the CPU with a RapidIO End.
• Designed for an FPGA to perform at-speed verification of the switch ASIC. This FPGA impersonatedmultiple clients and verified protocol as well as data integrity.
• Independently conceived and implemented a design change saving $1,000,000 annually by analyzing the resource utilization of a particular CPLD and re-targeting it to a much smaller and more appropriatedevice.