Brian Yuen Email and Phone Number

Silicon Validation | Optical and Linecard 10G, 25G, 50G, 100G Serdes Validation | FAE bringup expertiseI. Drove multiple interop projects for 50G and 100G optical products.a. Experienced with TOSA/ROSA optical sensitivity measurements, driver evaluation, and TIA evaluation.II. Created multiple test platforms in python for internal SerDes and PLL characterization as well as product sampling for customers.a. Experience with taking phase noise, jitter, BER, SNDR, HD2, HD3, and ENOB measurements.b. Wrote internal and customer SDK's in python from the ground up for product evaluation.III. Performed chip and EVB bring-ups for multiple optical and line-card products.a. Experienced with debugging software and hardware issues.b. Experienced with customer facing product bring-up flow.IV. Skilled in DCA oscilloscopes (electrical and optical):a. Proficient in TX TDECQ tuning, eye linearity optimization, jitter measurements, and waveform analysis.IV. Skilled in electrical lab equipment:a. Proficient with spectrum analyzers, temperature ramping equipment, signal generators, optical and electrical attenuators, optical and electrical scopes.

Ran Monte Carlo simulations for Credo's 28 and 16 nm chip through Cadence Virtuoso. Created lookup tables to facilitate analysis of our test points. Ran DC and AC analyses at transistor and block levels.

Working with a small group of motivated and independent engineers to design cutting edge, high speed SerDes. Primarily focused on optimizing clock synchronization accuracy using the phase locked looped model. Conducted simulations, using Cadence Virtuoso, that were focused on understanding how low to high frequency jitter affects closed loop and open loop PLL models. Determined the frequencies of jitter at which our PLL circuit suffered from its highest levels of attenuation.

I also work as a greeter at the Welcome Desk, a bouncer during group fitness classes, and an equipment manager for different sports supplies. Positions depend on the availability of me and my coworkers.

Utilized Cadence Virtuoso software to analyze and optimize phase locked loop circuits. Learned and tested the fundamental blocks of PLL circuit design such as: Voltage control oscillators, charge pumps, N dividers, and low pass filters.

Used BCM56150 PCB to run PVT tests for parameters ranging from cryogenic temperature to 120 Celsius. Analyzed the results to determine which high speed chip models needed to be revisited. Used an X terminal emulator for the KDE platform to perform data analysis.

Worked under Professor Cummings in the Computational Sensory Motor Systems Lab. Helped in developing a system of algorithms for 3D image processing that may later be applied to unmanned droids. Tested an arduino drone copter using GPS coordinates and manual controls.

Cooperated with administrators from the Fremont Unified School District and Tioga Energy Corporation to construct a Solar Power Purchase Agreement for Mission San Jose, providing the school sustainable energy through solar panels at no initial capital costs nor future operating costs. Bright Future Innovation Grant Gold Medal for $500 each year. Consecutive winner. Negotiated with Business leaders around the bay area for support and funding.

Writing for the opinion's section of the John's Hopkins Newsletter on the topic of internet privacy.

Conducted research under dean of engineering Osamu Ishihara on the effects of cryogenic conditions on complex dusty plasma. Received Siemens STEM Competition Semifinalist recognition for ensuing research paper.