Brian Box Email & Phone Number

Palo Alto, California, Us

San Jose, Ca, Us

ASIC ArchitectDeveloped context switching data driven programmable architecture for implementing DFE (Digital Front End) functions for cellular communications. Implemented Digital Pre Distortion, Crest Factor Reduction Digital Up Conversion and Digital Down Conversion functions.

Us

Led a team of five engineers through the specification, development, verification, fabrication, integration and documentation of a node of the QS2412 Adaptive Computing Machine ASIC. 400,000 gate node was developed with VHDL. Application focus included multimedia VL encode and decode for MPEG-4 and H.264, and communications encode and decode for WCDMA and 802.11a.

Us

Led a team of seven engineers through the specification, development, integration and documentation of 22 Xilinx Virtex, VirtexE and Spartan FPGAs and 27 CPLDs for optical networking applications.I developed 8 Xilinx Virtex, VirtexE and Spartan FPGAs and 7 CPLDs for optical networking applications using Verilog, Synplify and Modelsim. Supported the devices, with capacities up to 300,000 gates, were supported through board, software, system integration and customer delivery.

Founded and led a startup company which concentrated on FPGA development tools and design consulting.Led corporate planning and direction efforts, developed strategic alliances and partnerships, planned and directed product development, and represented the company at marketing meetings, demonstrations for customers and trade shows.Developed modules and FPGAs (Xilinx, Lucent, Lattice, Actel, Quicklogic and Altera) for processing and communications customers (AGFA, BBN, Hazeltine, Lockheed, Trancept Communications, Stanford Telecom, 3COM, Karma Systems, Iron Bridge Networks). Projects have included a GSM mini-tower, a digital receiver, routers, video processors, wireless telephony and other signal processing applications.

Bethesda, Md, Us

Ten years experience in module development which included module design, simulation, layout, release to fabrication, overseeing device procurement and assembly, debug, test and integration. Ten years experience in high performance FPGA development including: Xilinx, Actel, Altera, Pluslogic (now Xilinx), Quicklogic, Lattice and Lucent. Application areas included: Communications, Avionics, Electronic Warfare and processing. Responsible for FPGA development at Sanders which included providing training for all FPGA design engineers, leading the High Performance Team for FPGAs, evaluating and developing design tools and process for use by the company.Six years experience in technical leadership. Led teams of up to 13 engineers and technicians through the development of over 400 unique FPGA designs, 10 unique module designs and small software development efforts.Four years experience in administrative supervision. Interviewed candidates, led a group as large as 10 engineers, assigned responsibilities, oversaw the assignments, provided technical assistance, wrote reviews and oversaw career growth.Three years experience in program management. Managed programs which delivered hardware modules, software and documentation to customers and completed on-site integration for the customers. Targeted program capture, forecasted technology, wrote proposals and wrote white papers.

Msee, Electrical And Electronics Engineering

Bsee, Computer Engineering