Brian Whitehead Email & Phone Number

Ramsbottom, Gb

Home/Bristol/Plymouth

Cheadle

• Develop a Radiation Hard flow for Cadence Genus synthesis.• Synthesis of two macros in GF 22nm technology for a satellite communication IC.• Low Power Design with the Cadence Genus Synthesis

• Developing UVM test benches for memory controllers.• Create a System Verilog X3D memory controller PHY.• Set up fully automated regression verification suite for the Micron Manchester UVM tests suite using Mentors Verification Run Manager (VRM).

Sweden

Consultancy position working at ST-Ericsson Lund, Sweden.• Responsible for constraint development, synthesis and formal verification for two digital blocks within the modems division of ST-Ericsson.

Duisburg, Germany

• Consultancy position working in the Layout and Physical Synthesis department at Intel Mobile Communications in Duisburg Germany.• Responsible for synthesis of numerous blocks up to 2 million gates in size on a 40nm process.

. Founding member involving 8 month unpaid work.. Solely responsible for putting all the VHDL code produced by Virtensys through Synopsis Design Compiler to ensure it met physical design rules and STA criteria for external place and route.. Ensure all issues were resolved by close work with the place and route providers.. Targeted at TSMC 90nm technology and including IP from Virage Logic.. Responsible for the entire Virtensys FPGA tool work using Alterafs Quartus targeting the Stratix IV device.. Incorporated PCIe and transceiver IP.. Develop scripts to allow system architects to perform simple command line builds to produce programming files when their VHDL code is updated.. Capture of full top level chip in HDL Author for both ASIC and FPGA devices.

. Member of a physical design team responsible for the physical layout of a six million gate design for the Advanced Switch market.. Responsible for the synthesis and production of netlists for all top-level units of design of which many contained various IP blocks including RAM, using Synopsys Design Compiler.. Targeted at TSMCfs 0.18u high speed standard cell process.. Required the integration of third party IP blocks and their associated libraries into the DC flow. These included Artisan RAM and Register Files.. Multiple clock domains ranging from 100 to 250MHz.. Synthesis consultancy to all the design teams within Xyratex.. Perform initial place and route on top level blocks using Magma Blast Fusion physical design suite.. Determine the timing and area feasibility of the units of design.. Assist in the integration of the units of design into the top level.Philips

Providing CAD support to the design groups within Philips Semiconductors Zurich.• Development and maintenance of the DesignSync design data management tool from Synchronicity for over 150 users in a number of design teams from the Philips site in Zurich and sites in Ireland and Germany.▫ Resolve issues and problems from users.▫ Promote the correct use of the tools within the design teams.▫ Develop and promote efficient multi-site usage.

Manchester, United Kingdom

• Implementation of a multi-stage pipelined scheduling and arbitration algorithm in VHDL to be targeted at Fujitsu's 0.35u high-speed standard cell process running at a clock speed of 100MHz.▫ Write the hierarchical VHDL comprising of several thousand lines of code.▫ Produce a VHDL testbench for verification of the unit using Mentor's Modelsim.▫ Liase with Cadence to determine timing and physical constraints for synthesis using Cadence's Ambit synthesis tool and verify timing using Ambit's integrated STA engine.▫ Hand over netlist to Cadence for completion of place and route of the design and resolve any outstanding timing/physical issues.• Responsible for the synthesis and production of the netlists for a full chip comprising multiple top-level blocks of which many contained various IP blocks including RAM.▫ Targeted at Fujitsu's 0.35u high-speed standard cell process.▫ Multiple clock domains ranging from 100 to 250MHz.• Team leader responsible for the introduction of the digital physical design flow into Power X.▫ Targeted at TSMCs 0.18u high-speed standard cell technology using Nurlogic libraries.▫ Organised training sessions run by Cadence for a team of five on various tools and methodologies.▫ Schedule tasks and activities for the group.• Represented Power X at DATE in Paris 2000 and Munich 2001 and also DAC 2001 in Las Vegas.