Brian Bennett Email & Phone Number

Orange County, California, United States

Orange County, California Area

Irvine, Ca

Led program management of Integrated Project Teams through entire product life cycle, from concept to production. Managed direct reporting team of 50-100+ across architecture, design, validation. Delivered a product line of chipsets supporting the growth of Intel’s most profitable business segment (Data Center Group).

Irvine, Ca

Led high performing teams of engineers to design and implement a family of controller products used to expand MP Server memory capacity to >2TB. Direct responsibility for micro-architecture, RTL design, timing closure, performance, power. Working closely with matrix teams for circuit design, verification and validation. High visibility projects which met critically important schedules so as to not gate launch of Intel platforms and impact the associated CPU revenue stream.

Irvine, Ca

Designed dual channel memory controller and Buffer Management unit for Profusion chipset supporting 8-way SMP.Micro-architecture, Verilog RTL Coding, Timing closure, worked with external foundry LSI and IBM Microelectronics

Irvine, Ca

Manhattan Multi-Processor Server - AST's first high performance SMP server. • Designed the original 486 based CPU module which consisted of a 256 Kbyte second level copy- back cache, and a distributed interrupt control mechanism. • Responsible for specifying the system bus timing and clock skew design margins. • During bring-up of SCO UNIX port, provided technical and debug support to the O/S team.

Huntington Beach Ca

RISC Based Multiprocessor System - Designed a MIPS R3000 based avionics multiprocessor system. This design included external instruction and data caches of 64K bytes each. Cache coherency was maintained via a high performance invalidate logic scheme. Fault Tolerant Computer - Design engineer on a two man team which designed a high reliability fault tolerant computer system for use on the Delta launch vehicle. This system consisted of four Intel 80960MC processors running in lockstep, organized in a Quad Multiplex Redundant configuration.

Education record

Mba, Business Administration

Msee, Electrical Engineering; Emphasis: Digital Signal Processing

Bsee, Electrical Engineering