Team lead role (mentoring, leadership, and training) for 7 engineers.Implementation project manager for 65 million gate SOC in 28nm. * Managed schedules and deliverables for cross site teams in Canada and IndiaChip lead for 12 million gate 40nm ASIC for the printer market * Designed chip pad ring. Worked with customer to optimize pad ring and PCB interface. * Responsible for top level test clock definition and documentation * Responsible for updating and running top level IP tests for product engineering * Modified 32 bit DDR4 PHY to be only 16 bits to use less pads and less area. * Met customer’s tight schedule and delivered product with no functional or DFT bugsPower gating and power specification verification for 10 million gate SOC in 28nm. * Setup top level CPF * Ran Conformal Low Power to verify power intent matched post layout netlists * Created filter program in Python to parse and categorize violations

* Lead architect and logic designer for massively parallel multi-core processor arrays acquired from Ambric Corporation. * Logic designer of CABAC block for 65nm H.264 Encoder

* Architecture and logic design of L2 like RAM/cache block for Ambric's next generation of massively parallel processor arrays on 65nm. Design included a 2-way set associate synthesizable cache.* Architecture and logic redesign of RAM block for Ambric's next generation of massively parallel processor arrays on 65nm. Design includes several FIFO and RAM usage modes.* Responsible for several early design evaluations including process, standard cell, and EDA tool selections. Conducted early frequency, area, and power analysis studies.

* Architecture and logic design of L2 data prefetcher unit. Design based upon my patented original design.* Architecture and logic design of an upgraded Alias Hardware unit. Received patent on the architecture design.* Architecture and logic design of Victim Cache unit. Design was a major redesign for improved features and frequency.* Investigated and wrote proposal for FPGA emulation solution for system level pre-silicon validation.* Primary contributer and manager of the logic design methodology for Transmeta's next generation processor.

* Architecture and logic design on a 6.5 GB 4 channel PAM4 transceiver. * Designed a 16-bit 311Mhz microprocessor for handling configuration. * Designed and implemented control register bus, MDIO, and JTAG interfaces.* Managed validation effort including tests, coverage, and regressions.

* Logic design on Prescott Pentium® 4 project. Reponsible for RTL design of Address Generator Unit and for support logic for the Integer Register File.* Architecture and logic design on Tualatin Pentium® III project. Design lead for Data Prefetcher Unit. Implemented extensive redesign for critical cache speed paths and conducted Data Prefeetcher performance study.* Logic and architecture design on Coppermine Pentium® project. Design lead for on-die L2 cache controller.* Logic and circuit design on Deschutes Pentium® II project. Circuit redesign of L2 cache bus and main external bus data paths. Logic design of L2 cache controller enhancements.* Validation engineer on Pentium® Pro project. Responsible for micro architecture validation of bus units and validation of x86 architecture simulator.