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Brian B. Arceneaux is listed as Principle Engineer (Software| Machine Learning, Data, Ops) (Hardware| Storage - Memory, Semiconductors, Material Science) Productization, Design of Experiments, Research, PhD at Western Digital, based in San Francisco Bay Area, United States, United States. AeroLeads shows a work email signal at wdc.com and a matched LinkedIn profile for Brian B. Arceneaux.
Brian B. Arceneaux previously worked as Principal Engineer at Western Digital and Staff Engineer at Western Digital. Brian B. Arceneaux holds Phd, Nanotechnology / Semiconductor Materials / Economics/ Buiness Plan Writting from University At Albany.
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AeroLeads found 1 current-domain work email signal for Brian B. Arceneaux. Compare company email patterns before reaching out.
With over 10 years of experience spanning software development and nanotechnology research, I bring a robust background in designing experiments across both software and hardware domains, including semiconductor research, ReRAM, neuromorphic computing, machine learning, and distributed computing systems.At Western Digital, my current focus is on pioneering machine learning applications and robust data pipelines that bolster our container-as-a-service and VM offerings. In collaboration with my team, we’ve advanced our technological capabilities by optimizing ETL processes and developing sophisticated toolsets for data analysis. Our current initiative involves semi-supervised learning models that are set to revolutionize the way we approach complex data challenges.Leveraging a combination of Kubernetes, Python, and CI/CD, among other technologies, we’ve been able to enhance operational efficiency and drive innovation. My mission is to continue harnessing the power of AI to not only refine our product offerings but also to contribute to cutting-edge scientific research, ensuring Western Digital remains at the forefront of the storage solution industry.
Listed skills include Characterization, Physics, Nanotechnology, Matlab, and 32 others.
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San Jose, CA, US
Projects as Principle Engineer, Software Development (Apps)Current Projects: SV Calibration Data project, which leverages machine learning to continuously improve model performance while detecting anomalies. Key highlights of the project include: Initial Proof of Concept: Implemented supervised learning using a 1D Convolutional Neural Network (CNN) to.
San Jose, CA, US
Project Lead: GalaXY – Guided Data Discovery Platform Development – MVP1 o Tech Lead Engineer: Main roles included system design, web application coding to help build a scalable Dockerized microservice framework. This internally-built custom-web-application allows for UI (React) and API (curl) access to our internal big data platform. Typical Use Case.
San Jose, CA, US
o C-code Optimization: Developed a parallel-bit-testing algorithm in C-code for the in-house SanDisk (ReRAM) Test Vehicle, code was accepted for production-usage and reduced testing time by 20%o Statistical Testing / Circuit Simulations: CMOS Evaluation Study (CMOS TEG array + ReRAM cell). Developed the experimental design, characterized the voltage drop.
New York, NY, US
Pitched the first initial idea to upstate NY and NYC investors. Won first place in Albany Business plan competition.
San Jose, CA, US
Data Analytics, and Visualization (Volatile memory (SRAM, I/O Periphery FETS)) Technical Development Engineer, Staff - Developed binary search algorithm for transistor voltage-threshold calculation: Revived a thought-to-be-broken automatic wafer-test-machine; increased reliability testing productivity 100x (previous testing done manually before this.
San Jose, CA, US
Device Engr. NCG Researcher - Resistive RAM materials research (2 Patents accepted)
Albany, N.Y., US
Graduated in summer 2013.Dissertation title: Controlling the variability of hafnium oxide based non volatile resistive memory via the modeling of the switching process
Albany, N.Y., US
Electrical Characterization of ReRAM materials and crossbar,1T1R and array strucutres
Albany, NY, US
Memory Technologist 1T1R fabricationReRAM Reliability Materials/Electrical characterization of ReRAM XbarReRAM (Modeling Forming and Switching Phenomena via comsol and matlab)
www.bess-tech.com Acting-CEO (2010-11)Co-founderEnergy Technologist
Houston, Texas, US
I was a field engineer, responsible for running and troubleshooting down-hole measurement DSP based equipment
Quick answers generated from the profile data available on this page.
Brian B. Arceneaux works for Western Digital.
Brian B. Arceneaux is listed as Principle Engineer (Software| Machine Learning, Data, Ops) (Hardware| Storage - Memory, Semiconductors, Material Science) Productization, Design of Experiments, Research, PhD at Western Digital.
AeroLeads has found 1 work email signal at @wdc.com for Brian B. Arceneaux at Western Digital.
Brian B. Arceneaux is based in San Francisco Bay Area, United States, United States while working with Western Digital.
Brian B. Arceneaux has worked for Western Digital, Besstech (Battery Energy Storage Systems - Technologies) Llc, Cypress Semiconductor Corporation, Intermolecular, and Cnse.
You can use AeroLeads to view verified contact signals for Brian B. Arceneaux at Western Digital, including work email, phone, and LinkedIn data when available.
Brian B. Arceneaux holds Phd, Nanotechnology / Semiconductor Materials / Economics/ Buiness Plan Writting from University At Albany.
Brian B. Arceneaux is listed with skills including Characterization, Physics, Nanotechnology, Matlab, R&D, Semiconductors, Simulations, and Design Of Experiments.
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