Brice Servais Email & Phone Number

Grenoble Area, France

• Responsible of IP Verilog model development and verification.
• 28nm node analog design and physical implementation and verification (Design Rules Checks (DRC) / Layout Versus Schematic (LVS) and Design For Manufacturing (DFM)).
• In charge of library views generation and verification (liberty files, GDS, LEF …).

Grenoble Area, France

• Responsible to interface internal customer (based in India and Europe) to understand their needs in term of library CAD views.
• In charge of solution feasibility study, technical specifications definition and development follow-up.
• Responsible of library architecture implementation in 40 and 28 nm: Verilog model development, Timing generation, CAD views generation and validation (Mentor, Apache, Synopsys, Cadence).

Grenoble Area, France

• Consultant for ST-Ericsson
• Responsible to insure technical coordination among multi-site and multi-cultural teams on international projects (England, Finland, India, France).
• In charge to set up and support the digital environment to guarantee design tasks efficiency.
• Primary Interface of external IPs and CAD tools/Kits providers to insure a correct and stable design environment, bug and versioning tracking.
• Responsible to insure block timing characterization in top level context (ETM, ILM).

Grenoble Area, France

• Consultant for E2V Semiconductor
• Responsible to insure technical coordination among multi-site and multi-cultural teams on international projects (England, Finland, India, France).
• In charge to set up and support the digital environment to guarantee design tasks efficiency.
• Primary Interface of external IPs and CAD tools/Kits providers to insure a correct and stable design environment, bug and versioning tracking.
• Responsible to insure block timing characterization in top level context (ETM, ILM).

Crolles

• Consultant for STMicroelectronics
• In charge to follow-up several technologies design rules evolution to opportunely parameterized 3rd parties parasitic extraction tools (Synopsys Star RCxT, Mentor Calibre xRC).
• Responsible for R&D to validate through simulation new capacitance structure in CMOS065, CMOS090 and HCMOS9SiGe technologies.

Tours

• Consultant for STMicroelectronics
• In charge to code inside the Design Kits the technology design rules to be used by the backend verification tool (DRC, LVS checks, Post Layout Simulation (PLS)).
• In charge to interface the technology team to develop the parametric cell library inside the Design Kit.
• First level support for CAD related issues for internal customers.
• 3rd party EDA tools evaluation for parasitic extraction tool.

Ulm Area, Germany

• In charge of a feasibility study aimed at migrating a bipolar power circuit in MOS technology.
• Responsible for analog design and layout of the new structure

Master'S Degree, Microelectronics

Master'S Degree – International Curriculum, Microelectronics