Bruce Millar Email and Phone Number

1. ESD strategies for fabless chip and IP companies, including detail design and auditing. Training is also offered to companies that wish to develop in-house ESD design and layout capabilities.2. High-speed I/O design including automatic impedance control and equalization, specifically all DDR up to LPDDR4, but not limited to those. Other I/O’s have been LVTTL, PECL and HSTL.3. Precision timing systems incorporating clock-locked timing verniers. Developed primarily for high-speed IC testers, but now widely used to time high-speed PHYs. CMOS application achieves 10ps accuracy.

1. DDR I/O & ESD protection circuit design2. Porting DDR IP to multiple silicon foundries3. DDR IP customer application support (including layout audits)

1986-1990: ATE Design - Parametric Measurement Unit (PMU), Power Supplies & Pin Electronics,1990-2007: IC Design - ATE Pin Electronics ASICs(5), DRAM Memory, DDR SDRAM Interface IP.

1978-1983: Bromont (Que) Wafer Fab, Engineering & Production1983-1986: Kanata (Ont) Wafer Fab, Production

Development of production line IC testers for Bell telecom products.