Bruno Fernandes Email & Phone Number

Hamburg E Região, Alemanha

Coordination of activities, distribution and monitoring of work with the FPGA system teamEvaluation and integration of FPGA/ADC related solutionsCoordination of installation, firmware deployments, commissioning and support for MicroTCA and other FPGA based systemsCoordination of related activities which involve external groupsDefinition of MicroTCA and Team related workflows Developments and support of FPGA related solutions

Hamburg E Região, Alemanha

• Development of high-level uniform FPGA programming Framework for application development (Simulink, TCL/TQ);• Design of FPGA firmware, including modeling, synthesis, verification and implementation (ISE/Planahead, ModelSIM, Altera);• Automatic generation of FPGA configuration files via scripting (TCL/git)• Development and design (Specifications, Schematic Capture, Layout) of custom PCBs for high speed/throughput Boards (Altium, Eagle) ;• Integration, support and maintenance of externally develop projects;• Development of software for FPGA firmware development (TCL, Python, PyQt, C++);• MicroTCA platform support • Supervising and supporting students on related projects;

Lisboa E Região, Portugal

Responsible for the laboratory classes in Electronic Circuits and Digital Systems (1st year mandatory class for Physics, Biomedical and Biophysics engineering students)

Lisboa E Região, Portugal

Description in SideC hardware description language (develop by CoreWorks) of hardware models to implement a FFT core using co-prime factors algorithm, focusing on LTE telecommunications.Main tool used: Eclipse.

Lisboa E Região, Portugal

INESC Electronic Systems Design and Automation Research (ESDA) GroupAnalysis of the specification, timing constraints and implementation/development of VHDL modules to perform FFT, Interleaver, Puncture and Demodulator functions suitable for a UWB (Ultra Wideband) receiver based on MB-OFDM modulation. Validation in FPGAs.Target FPGAs: Xilinx Virtex-4 e Virtex-5.Main tools used: Emacs, Xilinx ISE 10, ChipScope 10 and Matlab.Project Ref PTDC/EEA-ELC/67993/2006Website of the Project: http://esda.inesc-id.pt/UWBR/

Geneva E Região, Suíça

Implementation, validation in laboratory and development of low-level software communication for the MICTP module level, a subsystem of the muon detector in the ATLAS experiment. Dissertation theme for Physics Engineer MSc degree.Target FPGA: Altera Stratix-II.Main tools used: Xemacs, Altera Quartus II (9.0), ModelSim (6.4a) and Synplify (C-2009.03).

Lisbon Area, Portugal;

Responsible for describing in VHDL, development and simulation of the MICTP module, subsystem of the muon detector of the ATLAS experiment (CERN).Work partially supported by FCT under the ATLAS Collaboration Experiment (CERN/FP/83551/2008) Physics Engineer BSc degree final work.Target FPGA: Altera Stratix-II.Tools used: Xemacs, Altera Quartus II (9.0), ModelSim (6.4) and Synplify Pro (9.6.2).

Mestre Engenharia Física, Física

Licenciado Em Engenharia Física, Física