Bryan Wang Email & Phone Number

ESD and Latch-up Testkeys DesignESD Devices Characterization,ESD Protection Scheme Design and Latch-up Prevention Design ESD and Latch-up Related Failure Analysis and Solutions Proposition Four international publications:"An EOS-Free PNP-enhanced cascoded NMOSFET structure for high voltage application"​, IRPS 2011."PMOS-triggered PMLSCR for high voltage application"​, EOS / ESD 2012."Enhanced PMOS-triggered PMLSCR with robust EOS immunity"​, IRPS 2013."A Non-typical Latch-up Event on HV ESD protection", EOS / ESD 2014.Patent Granted:US8253165, US8305721, US8345396, US8675322, US8748936, US8817436, US8901649, US9082620TW409930, TW409931, TW451560, TW422007, TW431885, TW485835CN660333, CN1048441, CN1219728, CN1442022, CN1694311, CN1696873Won 4 personal awards in annual competitions of Macronix.Other achievements:Wafer-level auto testing for Barth TLP system Build wafer-level auto testing latch-up systemBuild whole chip ESD simulation toolDesign and build a High-Z TDT vf-TLP system, includes building all the hardware and software.Other specialties:C / C++ programmingPython programmingEquipment control via GPIB and Ethernet interfaceHTBASIC programmingSPICE simulationTCAD simulation

Process reliability qualifications for developing process technologiesProduct reliability qualifications for the champion product of developing process technologiesFailure analysis for qualification failed items and improving plan providing.