Established the remote site for a VC-backed startup in Austin, TX. Assembled and led a team of digital and analog design and verification engineers building world-class low-power MCUs targeting AI/ML-at-the-edge applications.

Responsible for the development and execution of an implementation methodology for a MEMS-based digital microphone based on a Cadence tool design flow. Hands-on development of Genus and Tempus scripts and coordination of backend activities using Innovus for floorplanning / place / route.

Led the development of Ambiq's first-generation of low-power MCUs (Apollo). Managed the design from architecture through tape-out and contributed by creating the design methodology, RTL design of multiple subsystem components, and resolving issues through physical implementation. Additionally managed the site's IT resources and needs, recruited and on-boarded multiple team members and contractors, and engaged external suppliers of IP and design tools.

RTL development (including architecture tradeoffs, testbenches, and synthesis) of a protocol engine to facilitate a next-generation Intel-based PC motherboard chipset interface called CSI. Executed timing and logic ECOs for the MCP73 motherboard chipset. RTL development of a replacement on-chip bus protocol interface based on PCIe transactions. Verification of the Tegra T30 SoC memory controller arbitration schema. Redesigned the ALU unit of the Tegra graphics core (T20 product) to achieve higher computational throughput for integer and floating-point operations (architecture, micro-architecture, RTL development, verification, and synthesis). Optimization (RTL-level) of several units within the Kepler GPU core with a focus on power reduction (global and local clock-gating, synthesis/timing closure, and power analysis). Instituted methodology using Perl, HTML, and a database to track design metrics of area, performance, and power consumption.

Oversight of day-to-day operations of a $2M+ annual HVAC installation and service business. Manged employees, evaluated company value, and successfully negotiated the merger of the business with a similar competitor, maintaining positions for all existing employees in the process.

Led a team of seven digital design engineers responsible for the architecture definition, RTL implementation, and netlist delivery of a media processor SoC. Individual responsibilities included recruitment of new team members, allocation of architecture and design tasks, coordination across multiple teams both within and outside of the company (Marketing, Analog & Digital Design, pre-silicon Verification, post-silicon Validation, IP Vendors), and evaluation and review of individual team-member performance.

Primary lead of the design team responsible for a next-generation SoC platform (Sigmatel STMP3600). This product was specifically targeted at the MP3 player market, where cost and power consumption were primary concerns. Designed the on-chip and off-chip memory controllers (DRAM, NOR Flash, SRAM, ROM), internal buses, and DMA engines. Led the implementation of the FPGA emulation platform which was used to qualify the design and spent many hours in the lab testing and analyzing first silicon. Created the Verilog test environment enabling C-code testcases to be run. Worked to coordinate activities between the digital design team and the synthesis/layout teams to drive two chip tapeouts (synthesis and formal verification, timing closure, gate-level simulations, power simulations, ECOs). Evaluated IP for follow-on projects (STMP3700, STMP3800) including video, memory, and processor selection.

Worked as a team lead within a startup organization to architect and implement equipment for the next generation of video communication systems. Defined, specified, and implemented a custom FPGA design to perform video data routing duties within the system. This device included specialized image processing algorithms for a custom CMOS image sensor as well as video resolution scaling engines. Direct responsibility for chip architecture decisions, IP selection, specification/documentation, and implementation into an Altera Stratix FPGA with clock frequencies of 150MHz. Had decision making responsibility for the hardware development tools and methodology, FPGA vendor selection, ASIC foundry partner selection, and third party intellectual property selection (including DDR SDRAM, PCI, and chip interconnect methods).

Architected and implemented a PCI bus interface and a DDR SDRAM controller to be used in a Xilinx Virtex2 FPGA. Reviewed architecture specifications for an advanced DSP technology for high performance applications. Assisted with technical presentations for potential customers of consulting services

Architected, designed, and verified a high-performance DMA engine and memory interfaces for the BOPS ManArray family of digital signal processors. Responsible for system-on-chip assembly including internal bus structures (AHB and internal proprietary designs), external bus interfaces (MIPS SysAD and PCI). Visited customers and attended trade shows as a BOPS representative to provide technical support for the sales and marketing staff.

Verilog RTL development on multiple I/O interfaces for a VLIW DSP SoC (AC’97, IIS, IEC-958 (S/PDIF), and Sound Blaster hardware register support). Lead chip designer on a secondary ASIC product which included a PCI interface, complex DMA engine, and 14 multimedia I/O interfaces.

Co-lead engineer on a three-million transistor wavetable synthesizer product for PC audio applications. Partitioned DSP algorithms for hardware implementation, managed die layout and scheduling issues and overall chip simulation and verification plan.

Designed a software and hardware architecture to implement the Legacy Audio (e.g.: Sound Blaster) interface for the Mwave MDSP2780. Co-developed the architecture for a next-generation Mwave DSP.