An early hire on the new Cruise Silicon team (5th verification engineer, 2nd validation engineer). Helped grow teams by conducting interviews and hiring, defining team workflows, setting up compute infrastructure, training interns and new college grads, keeping up to date on my own knowledge, writing documentation, working with other groups at Cruise, and owning the most complex validation tasks.– Wrote tests in SystemVerilog/UVM and C for SoC modules: eFPGA, AXI targets/initiators, and DMA engine. Found and fixed bugs in our home-grown Python UVM generation scripts along the way.– Brought up, debugged, and validated a very difficult ethernet switch module on HAPS/VDK emulation and in silicon. Tested standard switch features plus PTP and 802.1CB. Wrote bare-metal C, linux driver code, and Python scripts for testing. Used Ixia extensively (GUI and python API).– Configured git repositories and build systems for our buildroot-based validation firmware for 2 chips– Led team of engineers to fully automate our validation tests using Python and the Labgrid framework

–Packaged and marketed Open Source Electronic Design Automation (EDA) software.–Full-stack development of online store using Python, Django, and Pure.css.

Part-time job coaching/mentoring senior engineering students as they completed their capstone engineering project. My team designed and built a soft robot arm to handle radioactive materials.

– Wrote C++ code to configure and monitor network daemons on the UniFi Dream Machine (router)

Second verification engineer hired. Helped grow team by conducting interviews and hiring, defining teamworkflows, setting up compute infrastructure, training others on the team in general verification techniques and on UVM and Python specifically, keeping up to date on my own knowledge, writing documentation, and taking the lead on complex projects.– Performed market research, presented to team and CEO, resulted in change of product focus and theacquisition of one of our first customers.– Wrote in C a small TLS 1.2 implementation targeting Intel NIOS processor. Can offload crypto operations and private key storage to FPGA. Automated testing against OpenSSL.– Wrote large portions of the embedded software build system using SCons (Python) and Buildroot.– Wrote mixed SystemVerilog UVM and Python testbenches for encrypt and decrypt modules and our coreTCP Inline Engine module. Used Python libraries such as cryptography, scapy, and twisted.– Convinced team to do code reviews and continuous integration, developed procedure for usingReviewBoard and Jenkins to do so. Defined team branching strategy as team git “expert.”

Same as before, just with SanDisk now after their acquisition of Fusion-io.

First verification engineer hired on team of 4 digital designers total. Helped grow team to about 20 people across 2 locations by conducting interviews and hiring, defining team workflows, setting up compute infrastructure, training interns and new college grads, keeping up to date on my own knowledge, writing documentation, working with other groups at Fusion, and taking the lead on complex testbenches.– Wrote SystemVerilog UVM NAND flash simulation model used to bring up and verify multiple NAND controller designs. Behaves as either ONFI or Toggle NAND. Easily customized according to vendor specs. Insignificant memory usage compared to 3rd party models. Randomized bit errors, response times, and dead chips. Wrote full suite of unit tests (SVUnit) to verify model correctness.– Designed full-chip SystemVerilog UVM testbench. Wrote host memory model, multi-layer AXI bus agent, interrupt handlers, completion scoreboard, uvm_reg adapters, transaction classes, low-level bus sequences, and high-level constrained random test sequences.– Automated code coverage collection and reporting with Python. Parsed code coverage reports, aggregated data into PostreSQL database. Wrote Python Flask web application to generate reports.– Wrote paper that was accepted for poster session at DVCon 2013: https://bryan-murdock.blogspot.com/2022/06/my-2013-dvcon-paper-and-poster.html– Integrated PCIe verification suite into our SystemVerilog testbench, root-caused many test failures due to configuration mismatches and specification non-compliance.– Wrote simulation and regression scripts in Python. Set up automated testing with Jenkins.

– Wrote C and C++ code for an RS-232 and I2C abstraction layer and TCP/IP network diagnostic tools.

– Wrote C++ for Edgline Multifunction Printer targeting PowerPC running Integrity RTOS, ASICs, and FPGAs. Implemented calibration, control, and monitoring algorithms for print-head electronics.– Performed system bring-up of electrical prototypes. Used data sheets, schematics, multi-meters, and oscilloscopes to debug full hardware/software system.– Wrote C++ code for the raster pipeline. Managed over 50 MB of imaging data in a multi-level caching scheme across three ASICs. Reduced algorithm memory use from 28 MB to 3 MB.

– Wrote a Linux/UNIX shell environment manager in bash/k-shell (similar to Environment Modules)– Researched, designed, and implemented assertion-based formal verification workflow using 0-in

Researched dynamic formal ASIC verification tools. Presented findings to large groups. Teams integrated the tools into their design flow. Exercised good UNIX administration knowledge to keep ASIC design tools running smoothly.

Wrote a Perl program to parse ASIC design and generate C code for accessing fields in ASIC registers.

Web development of static online course web pages.