Established and manage the Industries, Solutions and Ecosystems organization across the Siemens EDA IC verification business unit with the objective of identify key growth opportunities and driving innovate and differentiated solutions in strategic vertical markets (autonomous mobility, datacenter/HPC and aerospace & defense) and horizontal solution areas (AI/ML, cloud, FPGA, and functional safety)- Manage a global team of product/solution managers responsible for the entire solution lifecycle working in close collaboration with product teams, partner ecosystems and other divisions across Siemens Digital Industries Software- Initiated Siemens EDA entry into the autonomous mobility IC market by defining strategy, driving M&A and leading cross-company collaborations creating market differentiated solutions across the product portfolio- Thought leader defining strategies and driving innovation to move Siemens EDA products to the cloud and identifying opportunities to apply AI/ML to the IC verification productsResponsible for strategic planning and portfolio development across the Siemens EDA IC Verification business unit including defining broader strategies for long term growth and driving make/buy/invest/partner decisions to capitalize on those plans:- Initiated and drove multiple acquisitions to closure within the Siemens M&A framework including defining strategic rationale, sizing market opportunity, performing competitive analysis, conducting make/buy/invest/partner analysis, creating executive level pitch decks and developing financial models- Led marketing, go-to-market, business, product and technology due diligence efforts while collaborating with finance, HR, legal, IP, R&D, and sales across other due diligence workstreams- Drove and supported acquisition integrations for go-to-market, product management and R&D

Product Manager responsible for driving the business and associated products for the FPGA and functional safety markets. Responsible for the initiating the business unit's entry into the automotive functional safety market for ISO 26262.

Led and managed a multi-disciplined engineering team including design, verification, firmware and physical implementation developing IP and emulation/prototyping platforms for Enterprise SAS SSD’s:- Responsible for and supporting development of compression, encryption, PCIe application layer, flash channel and flash data path / virtualization IP blocks.- Responsible for defining, driving and technically leading SOC Palladium emulation and FPGA prototyping development flows and use models with a focus on improving efficiency, ease of use, automation and quality in order to minimize overall drive time to market.- Drove increased adoption of Agile methodologies using Rally and Jira.

Led and managed a multi-disciplinary hardware engineering organization in a fast-paced semiconductor start-up working closely with the software organization developing HPC and acceleration products integrating processing, networking, memory, and storage capturing all data coherently to be universally accessible to every application at hardware cache-memory speeds:- Drove entire hardware development lifecycle including product definition, product management, program management, architecture, modeling, design, verification, board design, chassis design, prototyping, validation, system integration, software integration and contract manufacturing- Primary contributor for competitive analysis and definition of disruptive technologies responsible for driving execution of development to executives and board of directors- Member of executive staff responsible for defining company strategy, seeking investment opportunities, pursuing M&A activity and exploring new development partnerships- Redefined company and product strategy with improved market adoptability, reduced development cost and improved time to market to enable increased scaling with new funding- Responsible for emerging technology investigations, methodology decisions, IP engagements, vendor interaction, and outsourced development efforts- Recruited, hired, managed and mentored a multi-disciplinary hardware engineering team in a rapidly evolving start-up environment that grew from 5 engineers to 35 engineers in 9 months- Project Manager responsible for defining, evolving, and leading the Agile and Lean development process of the hardware, software, and QA organizations with multiple parallel engineering efforts

Non-profit, member controlled organization responsible for directing the future development and driving adoption of RapidIO:- Interop Task Group Chair responsible for leading numerous RapdiIO Trade Association member companies in the development of the RapidIO Gen2 Interop Checklist. Redefined approach for better integration with modern verification techniques while improving coverage by 3x.- Active member within the RapidIO Trade Association serving as Xilinx's representative and primary contributor on key working groups including development of the Gen3 specification, next generation BFM, and interop checklist.

Self-driven, evolving role with continuously increasing technical and leadership responsibilities for development of critical Xilinx FPGA IP including Serial RapidIO (SRIO), QDR-II+, QPI, and PCIe IP:- Managed projects and engineers responsible for the entire IP development lifecycle- Verification lead for the Xilinx 20nm PCIe Gen3 hard block with a team of 10+ engineers- Manager and technical lead of the industry's first SRIO Gen2 6.25G FPGA solution driving $100M in annual revenue- Led deployment of the industry's first FPGA based QPI 1.1 solution by collaborating across divisions and partnering with Intel to create new Data Center and HPC opportunities- Architected and led design, verification, validation platform development, software integration, and hardware validation for the Virtex-6 QDR-II+ Memory Controller- Drove improved IP consistency and quality by leading globally distributed, cross-company teams to define and deliver improved IP development methodologies- Responsible for initiating, defining and leading Agile development efforts for FPGA IP

Factory facing applications role supporting FPGA 1G Ethernet, 10G Ethernet, and XAUI IP responsible for handling technical escalations from internal applications groups and top-tier customers; creating and maintaining customer facing documentation and collateral; collaborating with engineering and marketing to ensure customer focus; and training and continual development of application engineers.

Customer facing applications role responsible for supporting customers across the entire breadth of Xilinx solutions including all FPGA architectures, software, IP, design, synthesis, implementation, timing closure, hardware, verification and debug. Supported worldwide customer applications organization with specializations in high speed serial protocol IP, high speed serial transceivers, and configuration, in addition to, mentoring junior engineers.

Responsible for all facets of a joint farming operation including leasing land, financial management, equipment acquisition and maintenance, irrigation, planting, harvesting and other agronomics associated with growing corn and alfalfa. Also, managed a heard of 20 cattle.