Totally 20+ years professional experience as Analog, Mixed Signal IC layout engineer. With extensive experience in Finfet, CMOS and BiCMOS technologies.• Extensive experience in performing full custom Finfet/CMOS/BiCMOS layout from transistor level to top level.• Experienced and knowledgeable in using advanced very deep sub-micron technology nodes such as 90nm, 65nm, 40nm, 32nm, 28nm CMOS, and 16FF, 14FF, 7FF Finfet and 230nm BiCMOS TSMC/Samsung/GF processes.• Excellent technical skills and deep understanding of layout design issues and how to mitigate them such as the following:- Electro-migration- Latch-up- Antenna Effect- Electro-Static Discharge(ESD)- Cross-talk- Parasitics- Well Proximity Effect- DFM issues and othersExpertise:Layout/Design Tools:• Cadence Virtuoso XL• Cadence Virtuoso Layout Editor/Open Access• Cadence Virtuoso Schematic Composer• IC Craftsman (Virtuoso Custom Automatic Router)Verification Tools:• ASSURA, VerFlow LVS, DRC(Cadence)• Hercules LVS, DRC (Synopsys)• Calibre LVS, DRC (Mentor Graphics)*(Verification - DRC, LVS, ERC, RC Extraction, Antenna, DFM, EM and ESD check)Others:• Unix, Linux, Sun Solaris• MS office (Excel, Powerpoint, Word)• CitrixSpecialties:Full custom CMOS layout design of Analog and Mixed-Signal integrated circuits.DC-DC(power) chip, PLL, SERDES, USBOTG, USB 2.0, LDO, ADC, DAC, IO Buffers(GPIO, LVDS, MMC, LVCMOS & I2C) and test chips.Ethernet PHY(28GHz), DDR and HBMPHY