HoloLens display calibration.

I bring my full stack experience from C# application software through "bare metal" interface drivers in C/C++ down to Verilog/HDL and over a decade of experience with display hardware to the Surface media team. I am responsible for the architecture, design and implementation of software driving color accuracy across all Microsoft Surface products. My software is used in high volume manufacturing display calibration suites, verification and ultimately the shipping driver. I work within and across teams to engineer highly-capable cross platform solutions for Surface display quality. My solutions produce industry-leading color accuracy in Surface products whether the color space is sRGB or DCI-P3.Products I've been part of bringing to market include: Surface Studio; Surface Laptop; Surface Pro 2017; Surface Book; and more yet to come!

I bring my passion for new technology and my engineering skills to Microsoft Surface products. The work I do for Surface is incredibly exciting and I'm immensely proud of what we create here.I am principally responsible for Windows drivers, applications and software tools for Surface display technologies. This work includes: internal prototyping; high volume manufacturing verification; and drivers/services for retail devices on all Surface products. I also provide input on new hardware/silicon designs; OpenCL/Direct Compute SIMD kernels; build automation; and HW/SW debug expertise using tools from Windbg to JTAG.

As a member of the Operating Systems Group, I am involved in maintaining various Windows kernel components and device drivers for Windows 10's display kernel on both desktop and mobile platforms. Key responsibilities include: maintaining the Windows kernel display diagnostic tool; assisting with new high DPI monitor support in Windows 10; and enhancements and maintenance of software-based GPU emulation drivers and user interface application tools.

Power Management Validation / Software Infrastructure Expert. As technical lead for the embedded power management hard real time firmware validation on Xeon Phi "Knights Landing" product I was responsible for overall pCode validation and bringing forward innovative new validation tools for visualizing firmware execution in pre-Silicon simulation.

Component Design Engineer for next generation Many-Integrated Core (MIC) product, also marketed as Xeon Phi.

Senior Software Engineer, Power Management Architectural Validation in Intel's Many-Integrated Core Program. Responsible for technical readiness, design and development of test environments for design simulations; Providing C++ expertise for support of newly emergent simulation technologies; analysis, debug and root cause correlation of failures identified in simulation.Previous: Throughput computing validation group. Responsibilities include: micro-architectural validation, hardware debug, software engineering all the way through to "bare metal" programming, Linux system administration, and customer-focused cross-team interaction and training. Responsible for development and maintenance of a broad range of software products from productivity utilities and web applications to Windows & Linux device drivers (including WDF). I regularly use Python, C, C++, x86 assembly, Perl, Java, PHP and SQL - whatever it takes to get the job done.Prior to the throughput computing assignment, I worked in Discrete Graphics Validation as the senior Post-Silicon display validation engineer and chipset validation software tools engineer. Responsibilities included: full life-cycle software engineering, developing linux device drivers, embedded systems programming, C, C++, Lua, Assembly, Perl, Python, Ruby, debugging and troubleshooting, and linux system administration.