In the team of firmware and software engineers designing various parts of FPGA inVerilog/SystemVerilog, writing and debugging C/C++ code for communication with FPGA:- Implementing Digital Signal Processing algorithms for processing data in FPGA such asdigital down conversion, signal equalization and filtering, averaging of noisy data etc.- Capturing data from high speed ADCs.- Implementing/troubleshooting SDRAM memory controller (DDR3, DDR4).- Compiling FPGA (Intel/Altera Arria 10 GX, Stratix IV) with Quartus software, optimizingtiming and resource utilization in FPGA.- Writing testbenches, simulating with Modelsim.- Troubleshooting FPGA in hardware with SignalTap Logic Analyzer.- Fixing bugs and adding new features by customer’s request.- Doing code review, writing documentation.

- Developing quantiative models for air filtration in porous media in presence of electrical effects, developing computer codes (in C++ and Mathematica), performing model validation on experimental data.- Responsible for outsourcing applied research (aerosol physics, chemistry, microbiology) to academic partners such as G.K.Boreskov Institute of Catalysis SB RAS, V.V.Voevodsky Institute of Chemical Kinetics and Combustion SB RAS, the State Research Center of Virology and Biotechnology “Vector”, Novosibirsk Research Institute of Tuberculosis. - Responsible for obtaining a status of resident of Skolkovo Technopark for a spin-off of Airservice Co.Ltd. (ZAO Aerozaschita) with the project “Energy-efficient building ventilation systems”.- Responsible for starting physico-chemical laboratory at the Technopark of Novosibirsk Akademgorodok (www.academlab.ru)