Burt Cyr Email and Phone Number
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Product Development: Expert in embedded firmware development, SDK creation for various processors/FPGA, and debug of multicore systems for network switches (L2-7), virtualized micro services, video apps, telephony, storage and more; Languages/Tools: Expert in: C/C++, assembly language (see Silicon below), Bash, flex/bison, and Jira/Bitbucket/git. Knowledgeable in python, pexpect, HTML/CSS, and PHP. I created an EJTAG debugger for an 8-core MIPS with a GDB front-end. In-depth experience with boot-loaders, board bring-up, bus- and logic-analyzers, buildroot and docker. Can configure/support the tools/libs to support a tech village; wrote a framework for cont. integration via apache, python, php, css, html and pexpect. Skilled at creating small languages when needed using lex/yacc or leveraging Lua;Device Drivers Implemented/modified: custom FPGAs/ASICs; IPSec HW acceleration; flash memories, various sensors and IRQ handlers; PCIe-DMA driver for video stream analysis, various bus protocols: PCIe, SPI, MDIO and I2C;Network Architecture: Experienced with data-, control-, and mgmt planes; developing packet-walk software and SDKs;Network Software: Proficient in: RTP/TCP/UDP/IP/IPsec/QOS/OAM, NAT/Firewall, sockets, NW packet debug (layers2-7), high-perf design, CLI/SNMP MIBs and has assisted with html access and RESTful interfaces;Operating Systems: Expert in linux kernel/uspace, vxWorks, uCosII, IOT, pthreads. Can port these to new platforms. File Systems: Has written a custom reliable flash file system; is proficient with many open-source file systems;VOIP – Implemented VOIP infrastructure for soft-DSP features and related protocols; for low-powered environments;Bootstrap: Implemented custom boot-loaders and extended primary/secondary bootstrap. Brought up u-boot many times;Silicon: Experience with Cavium, Broadcom and Marvell SDKs; 32/64-bit: MIPs, PowerPC, x86, ARM, multicore; Team Management/Leadership: Good comm skills/team player. Promoted to manager within 6 weeks at one company.
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Sr Software Applications EngineerHolt Integrated Circuits Mar 2020 - PresentAliso Viejo, Ca, UsI create portable libraries (Application Programmer Interfaces) for a variety of cores, operating systems and bare metal applications typically in the MIL-1553 industry. I assist with architectural definitions and implementations that give Holt's customers latitude in their design decisions and how they wish to integrate Holt's silicon into their designs.
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Principal Software Development EngineerAperi Corporation Aug 2018 - Dec 2019I created the SDK libraries and low-level code for virtualized(docker) micro-service apps whose L2-4 data-planes were implemented in FPGA. These apps converted camera/video/audio feeds from ASI/SDI inputs into 1G/10G RTP dataflows using the Society of Motion Picture and TV Engineers (SMPTE) standards. They also converted from 1/10G to SDI/ASI;I specifically authored software (in C) for the following micro-service-based apps: Compressed/uncompressed media: SMPTE 2022-1,2,5,6,7; NAT/Firewall, Hitless Media Stream Merging and Failover; program discovery; I assisted with interfaces to pistache, and wrote a PCIe DMA module for transport stream parsing via tsduck. I crafted complete cross-tool (C/C++) and native SDK environments using buildroot for both the x86-64 and Arm;I configured the Aperi A1105’s Broadcom NPU for VLAN participation, tagging and PVID as appropriate;
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Software ArchitectRockley Photonics Inc. May 2016 - Jul 2018I helped design and implement the software (C+assembly) that demonstrated Rockley Photonics technology to potential customers: a CMOS-based L2,3 packet switch with bonded fibers (Topanga) each with 12 ports of 100G I/F; In one platform, 5 Topanga switches (1.2TB each) demonstrate a small folded-clos network for use in mega-datacenter applications. This had an Adlink Com-X (x86-64) module, which ran Linux and contained software drivers that could allow users to program the demonstration with different configurations;In a smaller platform, a single Topanga with a single PIC32 managed the demo. This ran an IOT-based OS (uCos/II) which I ported to support DFM, DFT, bring-up activities, and the mission mode of demonstrating L2-3 photonic networking;Both the 5- and 1-switch variant also had a Cypress Semi PSoC-5 CPU. I mentored a Caltech student to create a thermal mgr using a proportional-integral-derivative loop to keep the photonics operating within a tight temperature range;
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Principal Software EngineerRadian Memory Systems Mar 2015 - May 2016Calabasas, Ca., UsI designed and implemented: embedded SSD firmware (in C: IDT NUMA 16-core); Linux NVMe driver and PCIe DMA mods; RMS Symphonic Library mods to support a host-cooperative flash-translation-layer, statistic and trigger mgmt.; The firmware I produced also collected statistics of the drive’s low-level flash performance to manage garbage collection and wear-leveling activities for longevity. It provided trigger creation and asynch notification to avoid user polling; I developed a regression framework using: apache, ssh, web power switches, PHP, python+pexpect, and html/css; -
Principal Software EngineerAerohive Networks Oct 2012 - May 2014Milpitas, Ca, UsResponsible for bring-up and development (in C and ARM assembly) of Aerohive’s L2,3 switch platforms, kernel and drivers for control+ data-planes, bootrom, 10G/1G MAC and Phy drivers. A key contributor to the HiveOS (linux-based) platform team; I developed a good working knowledge of Marvell’s data-plane and Core Prestera Software Suite while working with Marvell’s Bobcat 41xx CPU as well as the 2140 and 2242 PHY chipsets;Helped author and debug several significant components of the bootstrap process related to this activity. -
Member Of Technical StaffCanoga Perkins Corp. Aug 2011 - Sep 2012Chatsworth, California, UsI developed software (in C) for the 9145E Large Building Ethernet Aggregation Switch. This provisioned L2: IEEE 802.1Q; Ethernet OAM, performance monitoring, flow policing and shaping, link loss forwarding, SNMPv1-3 Mgmt., and Metro Ethernet Forum compliance – all providing 5-9’s reliability;Six weeks after joining, I was given the responsibility for managing the S/W group. -
Principal Software EngineerXirrus Jul 2010 - Jul 2011San Francisco, California, UsResponsible for tool-chain development, board bring-up (u-boot) and development of next gen high-perf Wifi systems;Developed multi-core L2,3 software (in C and assembly) for Cavium 52xx/63xx and Atheros radios; kernel and drivers;I also developed a kernel trace utility to provide for post-mortem analysis and ported Oprofile for perf. analysis; -
Software ArchitectAlcatel-Lucent Sep 2006 - Jun 2010Espoo, Southern Finland, FiDeveloped (in C) proprietary Ethernet packet flow-scheduling software for L2,3 data-plane forwarding in ALU’s routers;Developed a 0-copy/0-context-switch HW crypto data-plane driver for Freescale’s SEC 2.0 crypto engine. (Note: my driver exceeded the benchmarks of Freescale’s whitepaper which used the Talitos distro on the same core);Responsible for software design, board bring-up and development of enterprise, access and gateway products;Developed Linux drivers for nand/nor/compact flash, USB and hardware crypto devices; Helped select next-gen switch and silicon processors using Kepner-Tregoe analysis;I developed a good working knowledge of Broadcom’s Strata-XGS SDK while working on ALU’s routers; -
Sr. Software EngineerD2 Technologies Apr 2004 - Apr 2006UsI designed/developed D2’s RTOS architecture (vPort) to ease porting of voice software and algorithms to new RTOS platforms in bandwidth-constrained CPU architectures (250MHz and below);Developed software (in C) for VOIP/RTP/SIP on MIPS and ARM 920T platforms for VxWorks, Linux and Nucleus;Performed interoperability, network impairment, voice quality test scoring (Malden) to improve product quality. Helped optimize voice algorithms through cache-conscious programming methods and analysis. -
Sr Software EngineerFulcrum Microsystems Apr 2002 - May 2003Calabasas, Ca, UsPorted VxWorks/Linux to an 8-core MIPS SOC.Developed an EJTAG debugger based on GDB.Developed a custom BSP for Fulcrum's MIPS processor. -
Sr Software EngineerExtreme Networks Mar 1999 - Mar 2002Morrisville, Nc, UsDeveloped router applications, Extended Kernel for multi-core MIPS and Debug.Designed and implemented RTOS kernel and bootrom extensions to support multiple MIPs CPUs in Extreme’s Network Switches. This provided inter- and intra-CPU: task communication, concurrent CPU interrupt handling, task scheduling and synchronization. These included: inter-CPU semaphores (3-types); message passing (copy and zero-copy); an memory allocation package to replace the standard VxWorks library; a shared-variable and a shared-memory library. I implemented a memory manager and leak monitor to limit and verify memory use on a per-task basis. Also included was a memory verification routine used to debug memory corruption. -
Principal Software EngineerXylan Oct 1993 - Mar 1999Tech lead in the implementation of the software architectures for the OmniSwitch (Any-to-Any Vlan switch) and OmniCell (ATM cell-switch); I selected and ported the bootstrap and RTOS (vxWorks) and performed its bring-up; implemented L3 routing (PNNI) on the Omnicell; I also implemented management plane MIBs (using ASN.1) for all;I wrote (C and assembly): Ethernet drivers, ARP, brought up vxWorks’ TCP/IP, ported telnet clients and servers, wrote a reliable memory-mapped flash file system, and created an on-board configuration library and database;Assisted with design/development of Xylan’s VLAN architecture which interfaced to Xylan-proprietary ASICs, implemented significant parts in C and sparclite assembly;Ported Epilogue’s SNMP agent (V2-compliant) to vxWorks/Sparclite and implemented the top-level and first Xylan MIBs;I implemented shared object loading from compressed object files for patching a running system without reboot (prior to dynamic loading being available from vxworks or linux);
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Lead Software Engineer, ManagerAscom Timeplex Feb 1992 - Oct 1993Us• Responsibilities included the development of the OSI routing protocols: CLNP, ES-IS and IS-IS for the Timeplex family of routers. I lead a small team to facilitate this.• Managed the efforts of over 50 software developers and coordinated with SQA to ensure timely S/W releases.• Represented Ascom Timeplex in ANSI (X3S3.3 and X3T5.4), IETF and NIST standards committees. -
Software EngineerRetix, Inc Jan 1987 - Feb 1992• Designed and developed portable-C software modules which implemented different OSI protocols. In the Application layer, I designed and developed the Remote Operations Service Element (ROSE) and the Association Control Service Element (ACSE) protocols. I also assisted with the File Transfer, Access and Management protocol. • In the Network layer, I developed a NetBIOS conformance tester for Retix’ Adapter cards and NetBIOS software. • Represented Retix at the National Institute for Standards and Technology.
Burt Cyr Skills
Burt Cyr Education Details
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California State University, NorthridgeComputer Science -
Brooks Institute
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California State University, NorthridgeComputer Science
Frequently Asked Questions about Burt Cyr
What company does Burt Cyr work for?
Burt Cyr works for Holt Integrated Circuits
What is Burt Cyr's role at the current company?
Burt Cyr's current role is Principal Software Development Engineer.
What is Burt Cyr's email address?
Burt Cyr's email address is bu****@****zon.net
What schools did Burt Cyr attend?
Burt Cyr attended California State University, Northridge, Brooks Institute, California State University, Northridge.
What skills is Burt Cyr known for?
Burt Cyr has skills like Embedded Systems, Device Drivers, Ethernet, Linux, Snmp, Tcp/ip, Vxworks, Debugging, Firmware, Rtos, Linux Kernel, Wireless.
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