I am a Computer Engineer working with DFT (Design for Testability) on ASIC projects. I have experience mainly with MBIST, mostly insertion and verification. Furthermore, I also have experience with some post-silicon validation activities, developing software routines in order to validate the chip integrity after the packaging.During my masters degree in Computer Science and Computational Mathematics at ICMC-USP, I gained a good experience in HFT (High Frequency Trading) field. My project proposed an FPGA-based hardware component for market data decoding in low latency. The component was developed to parse market data messages based in FAST (FIX Adapted for STreaming) protocol, to FIX (Financial Information eXchange) protocol messages. Therefore, assembling and outputting the order book. The parser was based in B3 template rules, which is the Brazil Stock Exchange.I have prior experience with:• Embedded systems.• Embedded software.• Firmware development in C and C++, having already worked with STM32, Analog Devices, Arduino, and ESP. With arm core and others architectures. • FPGA-based hardware development in VHDL and Verilog, having already worked with Intel Altera using Quartus and ModelSim. Also, with Active-HDL. • Impedance analysis and Fast Fourier Transform (FFT).• Software development in C, C++, and Python.