Alessandro Caratelli

Alessandro Caratelli Email and Phone Number

PhD | Digital IC Design | Staff Engineer at CERN @ CERN
genève, geneva, switzerland
Alessandro Caratelli's Location
Geneva, Geneva, Switzerland, Switzerland
About Alessandro Caratelli

Alessandro Caratelli is a PhD | Digital IC Design | Staff Engineer at CERN at CERN. He is proficient in Spanish, French and English.

Alessandro Caratelli's Current Company Details
CERN

Cern

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PhD | Digital IC Design | Staff Engineer at CERN
genève, geneva, switzerland
Website:
cern.ch
Employees:
5852
Alessandro Caratelli Work Experience Details
  • Cern
    Digital Architecture Design - Risc-V Based Soc
    Cern 2023 - Present
    - R&D on Radiation-Tolerant RISC-V-based SoC architectures.- Implementation and maintenance of automation tools for hardware and embedded software generation.- Study SoC architectures to optimize and identify areas that require fault-tolerance and radiation tolerance by design.
  • Cern
    Digital Ic Design And Physical Implementation Engineer
    Cern 2015 - Present
    Geneva, Switzerland
    Digital design, physical implementation and signoff of 5 different digital-on-top ASICs and several other IP blocks in 65nm and 28nm technologies:– RTL design (Verilog / System Verilog)– Synthesis and physical implementation (RTL to GDS): · Constraints and power intent · Synthesis · Scan insertion · Static Timing Analysis and Timing Closure · Floor-planning · CTS · Place and Route flow · Signal integrity · ECO operations · Power analysis, IR drop and EM verification · Analog IPs integration · Physical verification– Intensive usage of low-power and radiation-aware techniquesVerification, simulation and modelling at block and at chip level: - Test-bench architecture definition and verification planning - Good experience in constrained-random verification environments implementation in System Verilog / UVM, including design of verification components, stimuli generation, coverage
  • Cern
    Digital Ic Design
    Cern 2020 - Present
    Geneva, Switzerland
    Main design engineer for a pixel detector readout ASIC: coordinating and directly contributing to the requirements definitions, digital design, physical implementation, signoff and testing of the IC. System definition studies and optimization of the electronic system architecture.
  • Cern Asic Support & Foundry Services
    Eda Tools And Technology Support Coordination
    Cern Asic Support & Foundry Services 2021 - Present
    Geneva, Switzerland
    Coordinating the ”CERN Technology Support service”:– Establish and maintain relationships with EDA software tool providers, IP vendors and silicon foundry intermediaries.– Design support for about 80 European Research Institutes and Universities part of the high-energy physics collaborations.– PDKs maintenance (with radiation tolerance features).– Preparation and distribution of design flows, scripts and IP blocks.– Provide support for the projects facing issues with EDA tools, design kits, radiation hardened design practices and sign-offhttps://asicsupport.web.cern.ch
  • Cern
    Research Intern
    Cern 2013 - 2015
    Geneva Area, Svizzera
    RTL Design and Implementation of a multi-purpose radiation tolerant control and monitoring DSP used by multiple physics experiments including ATLAS, CMS, LHCb and ITER.

Alessandro Caratelli Education Details

Frequently Asked Questions about Alessandro Caratelli

What company does Alessandro Caratelli work for?

Alessandro Caratelli works for Cern

What is Alessandro Caratelli's role at the current company?

Alessandro Caratelli's current role is PhD | Digital IC Design | Staff Engineer at CERN.

What schools did Alessandro Caratelli attend?

Alessandro Caratelli attended Ecole Polytechnique Fédérale De Lausanne, Università Di Pisa, Universidad Carlos Iii De Madrid, Università Di Pisa.

Who are Alessandro Caratelli's colleagues?

Alessandro Caratelli's colleagues are Giacomo Broggi, Mark Tweenko, Jake Pfaller, Kalioppe Redd, Yixiao Han, Alexi Mestvirishvili, Pavan Chaganti.

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