Alessandro Caratelli Email & Phone Number

- R&D on Radiation-Tolerant RISC-V-based SoC architectures.- Implementation and maintenance of automation tools for hardware and embedded software generation.- Study SoC architectures to optimize and identify areas that require fault-tolerance and radiation tolerance by design.

Geneva, Switzerland

Digital design, physical implementation and signoff of 5 different digital-on-top ASICs and several other IP blocks in 65nm and 28nm technologies:– RTL design (Verilog / System Verilog)– Synthesis and physical implementation (RTL to GDS): · Constraints and power intent · Synthesis · Scan insertion · Static Timing Analysis and Timing Closure · Floor-planning · CTS · Place and Route flow · Signal integrity · ECO operations · Power analysis, IR drop and EM verification · Analog IPs integration · Physical verification– Intensive usage of low-power and radiation-aware techniquesVerification, simulation and modelling at block and at chip level: - Test-bench architecture definition and verification planning - Good experience in constrained-random verification environments implementation in System Verilog / UVM, including design of verification components, stimuli generation, coverage

Geneva, Switzerland

Main design engineer for a pixel detector readout ASIC: coordinating and directly contributing to the requirements definitions, digital design, physical implementation, signoff and testing of the IC. System definition studies and optimization of the electronic system architecture.

Geneva, Switzerland

Coordinating the ”CERN Technology Support service”:– Establish and maintain relationships with EDA software tool providers, IP vendors and silicon foundry intermediaries.– Design support for about 80 European Research Institutes and Universities part of the high-energy physics collaborations.– PDKs maintenance (with radiation tolerance features).– Preparation and distribution of design flows, scripts and IP blocks.– Provide support for the projects facing issues with EDA tools, design kits, radiation hardened design practices and sign-offhttps://asicsupport.web.cern.ch

Geneva Area, Svizzera

RTL Design and Implementation of a multi-purpose radiation tolerant control and monitoring DSP used by multiple physics experiments including ATLAS, CMS, LHCb and ITER.

Phd, Microsystems And Microelectronics

Master Of Science - Ms, Electrical And Electronics Engineering, Full Marks, Cum Laude

Electrical And Electronics Engineering

Bachelor Of Engineering - Be, Electrical And Electronics Engineering, Full Marks, Cum Laude