Always open to consider new opportunities in the field of failure analysis, quality, product engineering and design.Hands-on technical expert with 14 years experience in Failure Analysis groups assisting design, product development, yield, qualification, and customer returns of cutting edge (90 nm) logic, analog and mixed signal designs using CMOS, GaAs and SOI technologies. A successful track proven failure analyst. Employs CAD(CADENCE - ADS) fault simulation to isolate failure mechanisms. Familiar with DFT methodologies Memory BIST and ATPG. I have used Knights/Camelot design database for analysis of integrated circuits. Multilingual with fluency in English and Spanish (native).Specialties: Innovation, Leadership, Planning, Communication, Presentations, Customer Focused, Problem Solving, Analytical, Quality Management, Advanced Failure Analysis Techniques, Digital, Analog and Mixed-Signal IC Troubleshooting, ATE, CAD-ADS Fault Simulations, Semiconductor Technologies, CSAM, X-RAYS, BENCH TEST (MultiTrace, Curve Tracer, Semiconductor Analyzer, Network Analyzer, Spectrum Analyzer), NISENE JetEtch, FALIT Laser Decapsulation, Liquid Crystal, TIVA, XIVA, RIE, Wet Chemistry, SEM (JEOL 6400, HITACHI S4700), EDX.Very interested in group theory, symmetry, and representation theories.
Listed skills include Failure Analysis, Semiconductors, Cmos, Sem, and 18 others.