Casey Cooper Email & Phone Number

• Responsible for the execution of Digital Engineering (DE) support activities, to include Model-Based Systems Engineering (MBSE), and the management of INTUITIVE's MBSE Collaboration Center laboratory.• Currently leads a team of Model-Based Systems Engineers and coordinates with Army research and development communities across Redstone Arsenal to provide engineering and analysis services to Army aviation and missile products.

• Managed a team of engineers and analysts focused on developing reliability analytical methods and tools to identify top drivers contributing to decreased reliability of Army aviation and missile systems and the contributing part, material, and/or process to system failures.

• Managed STI’s Engineering Group and the Microelectronics ISO Class 6 Cleanroom laboratories.• Performed Design for Manufacturability (DfM) studies to ensure product overall design compliance with IPC-2222, land pattern compliance with IPC-7351, and system-level manufacturability.• Awarded three MDA SBIR Phase I contracts as Principal Investigator with three successive Phase II contracts to design, develop, and deliver prototype assemblies utilizing STI’s Imbedded Component/Die Technology (IC/DT®) packaging technology to meet size, weight, and power constraints for various Missile Defense Agency (MDA) platforms.• Demonstrated STI’s chip-in-board packaging technology (IC/DT®) to TRL 8 through a prototype that was integrated into a Standard Missile-2 (SM-2) flight test that was successfully conducted at Point Mugu, California on October 10, 2007.• Developed a custom materials qualification test protocol utilizing a modification to standard Surface Insulation Resistance (SIR) test procedures that offers an accelerated method to qualify assembly materials and processes for high reliability electronics hardware operating in harsh environments.• Identified, evaluated, purchased, installed, and operated manufacturing equipment to assemble microelectronic assemblies using a new chip-in-board packaging technology.• Managed the engineering design, materials selection, construction, installation, and validation of an ISO Class 6/Class 1000 Cleanroom facility in STI’s Microelectronics Laboratory.

• Assisted in design of a MEMs based micro-cooler for electronic cooling.• Participated in redesign of multi-chip module LTCC layout.• Developed IGBT matching test circuit.• Designed circuit for operating two IGBTs in parallel.• Gained personal and research skills through working with senior electrical engineers, engineers from varying fields, and technicians.

• Gained valuable research skills through working with graduate students and other engineers in industry on various projects.• Developed a process for flip chip-on-laminate to be used for under-the-hood automotive applications.• Experimented with various underfills for increasing the reliability of the flip chips during thermal shock testing.• Conducted failure analysis to determine the failure mechanisms of the flip chips.• Operated and maintained automated assembly and packaging equipment for graduate research projects and CAVE funded projects.• Received the Frank Vandergrift Award - Auburn University’s Outstanding Engineer Co-op.

Master Of Science In Engineering - Mse, Systems Engineering

Bsee, Electrical Engineering, Summa Cum Laude

Activities and Societies: Institute of Electrical and Electronics Engineers, IMAPS, Eta Kappa Nu, Tau Beta Pi, Phi Theta Kappa, Cupola.