• "Über Tech Lead" for Hardware Tools in Core, 2022-01 to 2024-04.• Founded "Accelerated Hardware Synthesis" (XLS, github.com/google/xls): an open source project to cross-pollenate software engineering and hardware engineering capabilities in the "End of Moore's Law" era (2018-12 to 2024-04).• Founder of / Tech Lead for XLA (Accelerated Linear Algebra compiler), a domain specific compiler for ML algorithms; from its inception to 2018-12. Originally built it for use on GPUs, proposed its use as the primary programming interface of the TPUv2+. TL of compiler / runtime / codesign-simulation software for TPUv2. Codesigned XLA:TPU backend with the TPUv2 hardware/ISA. Built the foundations of the TPUv{2,3} runtime and the first-cut TensorFlow integration.• Built StreamExecutor runtime to abstract over kernel-launching event-recording runtimes - built the foundational StreamExecutor support for CUDA, OpenCL, and TPUv1.

Worked as a platform technology generalist, with cross-stack work including: Linux kernel spelunking, extending capabilities on the bare-metal management-engine side of the machine, and implementing SIMD codes for ARM NEON units.

Worked on the internals of the SpiderMonkey JavaScript virtual machine and its compiler subcomponents: TraceMonkey, a tracing JIT, and JägerMonkey, a whole-method (local) optimizing JIT, and IonMonkey, a whole-method (global) optimizing JIT.Implemented, analyzed, and optimized the engine on supported architectures (x64, x86, and ARM), from the frontend (parser/emitter) through to optimization/deoptimization/runtime functionality and all the way down to code generation.

Performed software design and implementation of compiler back-end components for the Project Denver CPU.Assisted with the implementation of a realtime column-oriented database for performance data collection and analysis.Worked with Just-in-Time compilation and dynamic binary translation.Designed and developed RTL-instrumenting performance analysis software in C++ for use in chipset IP development.

Researched hardware protection mechanisms for critical heap data in type-unsafe languages (with a focus on C++).

Worked with chipset architecture, ASIC design methodology, architectural simulation, and chipset-related protocols assisting with the development an IOMMU unit.