Cédric Pujol Email & Phone Number

Paris Area, France

• Product manager for EEsof RFIC products including GoldenGate, Momentum, FEM, Heatwave and ADS for Silicon RFIC design• Responsible for relationships with Silicon Foundries

Paris Area, France

• Responsible for Keysight EEsof Device Modeling activities in EMEA• Technical account management for Keysight EEsof portfolio for key accounts and research centers• Consulting activities for major accounts

Paris Area, France

• Responsible for Agilent EEsof Device Modeling activities in EMEA• Technical account management for Agilent EEsof portfolio for key accounts and research centers• Consulting activities for major accounts

Orléans Area, France

• Managed all European and Israeli accounts for Xpedion’s GoldenGate simulator• Worked closely with prospects and customers to understand their needs• Worked closely with Xpedion sales and engineering to ensure the GoldenGate product was well-aligned with customer needs• Made technical pre and post-sales presentations of GoldenGate capabilities to prospects and customers.• Provided remote and on-site technical support and trainings to users.• Developed application materials which would assist in communicating the products strengths to prospects and customers and help them to apply state-of-the-art simulation techniques

Grenoble Area, France

• Defined the RF tools strategy for all ST divisions and external customers, including the selection and evaluation of new RF tools, close relationships with the RF EDA vendors to define new specifications for the existing tools in order to provide ST designers and customers with a best in class RF tools offer• In charge of testing on a BICMOS WCDMA receiver the implementation of the Analog and Mixed Signal extensions of the major digital simulators• Responsible for defining a methodology for substrate noise analyses.• In charge of the post layout simulations flow of RF analog and mixed signal systems on chips.

Grenoble Area, France

• Supervised design kits development for ADS• Worked with ST design teams to deal with the simulations of full RF analog and mixed signal systems on chip : set up a methodology based on Agilent to simulate a CMOS satellite tuner described at different abstraction levels using several languages: Ptolemy, C, Matlab for data flow, VHDL, Verilog for digital, behavioral models and transistor netlists for analog RF.

Grenoble Area, France

• Worked closely with all the major EDA vendors (Cadence, Mentor, Agilent and Aplac Solutions) to improve their RF offers, and tested their solutions on all the classical RF analog designs• Created and promoted the ST RF flow• Developed and improved ADS design kits for all the RF (CMOS and BICMOS) technologies supported by ST

Paris Area, France

• Developed Matlab and Visual Basic routines to drive antennas from remote• Developed programs to interface softwares and hardware equipments to measure and analyze ambient noise in the telecommunications emission bands