Chaitrali Joshi Email & Phone Number

Santa Clara, California, United States

San Francisco Bay Area

Portland, Oregon Area

Portland, Oregon Area

Pune Area, India

⦁ Performed SoC level verification for peripherals SFC, UART, I2C, watchdog timer, GPIO, temperature and voltage sensor. Wrote integration tests to check functionality and achieve 100% functional and code coverage⦁ Developed uvm environment for interrupt verification and wrote system verilog assertions to check the functionality of interrupt glue logic⦁ knowledge of UVM register modelling and wrote sequences and tests for register stress testing⦁ Performed gate level simulations for the peripherals and debugged issues in the netlist⦁ Did testbench development for subsystem level verification of GPU, video encoder and decoder Developed verification plan, portable C tests to deliver for SoC level, regression setup, system verilog assertions for functionality checks, integration of VIP monitors⦁ Updated existing C shell scripts to generate test lists and verification plans from IP delivered test suites to match new flows⦁ Knowledge of AXI and APB protocolsTraining completed - ⦁ system verilog language for verification (Cadence India)⦁ system verilog advanced verification using UVM 1.1 (Cadence India)⦁ system verilog assertions (Caence India)

Master'S Degree, Computer Engineering, 4.0/4.0

Bachelor'S Degree, Electronics And Telecommunication, 9.02/10