Verification Engineer, have completed Masters specialized in VLSI Design and Embedded System from CMR Institute of Technology, Bangalore, Karnataka. Skills:-Have experience in both IP level and Soc level Verification.HVL - UVM, System VerilogHDL - VerilogSccripting Language - PERL, ShellTools - Synopsys VCS, Cadence Incisive, Mentor-Questasim, Perl and Xilinx.