[Jan. 2014 ~ Aug. 2016]Development of the Broadcasting Receiver for the ATSC 3.0- Development of C Model + Type B LDPC Decoder + Integration of RX C Simulator- RTL Design / RTL Simulation & Verification + Type B LDPC Decoder, BCH Decoder, LDM Processing Block- FPGA Synthesis and P&R, FPGA Test & Debugging[Sept. 2009 ~ Dec. 2013]Development of the Broadcasting Receiver for the DVB-T2/C2/S2 - RTL Design/ RTL Simulation & Verification + LDPC/BCH Decoder + De-mapper block + BDI (Bit De-Interleaver) block + SISO and MISO (SFBC) Block- Integration of BICM (Bit-Interleaved Coded Modulation) Part & Verification- FPGA Synthesis and P&R, FPGA Test and Debugging- Pre-Layout/Post-Layout Simulation[Mar. 2008 ~ Aug. 2009]Development of the Mobile Broadcasting Receiver for ATSC-MH- RTL Design/ RTL Simulation & Verification + Channel Estimator Block- FPGA Synthesis and P&R, FPGA Test and Debugging- Pre-Layout/Post-Layout Simulation [Mar. 2004 ~ Feb. 2008]Development of the MODEM SoC for Wibro/WiMAX (Wireless Communication Standard)- RTL Design and Simulation/ Verification + STBC (Space-Time Block Code) block + CPU bus system using ARM1136JS + MPMC (ARM PrimeCell PL302) block (Multi-Port Memory Controller)