My Ph.D. research focused on the analysis, design, implementation and characterization of front-end ASICs for 3-D medical ultrasound imaging. Dissertation: “Front-End ASICs for 3-D Ultrasound: From Beamforming to Digitization” Main achievements: 1. The first full-matrix front-end ASIC enabling in-probe digitization with <1mW/element power efficiency Published in: ISSCC-2018 (Press-kit highlight), IUS-2017 (Best student paper), JSSC-2018(Nov.)2. The first reported 2-D array front-end ASIC integrated with 1000+ transducer elements, realizing analog subarray beamforming with record RX power-efficiencyPublished in: VLSI-2016 (Press-kit highlight), JSSC-2017(Apr.), PMB-20183. An efficient approach for direct PZT-on-CMOS integration and its experimental demonstrationPublished in: TUFFC-2016 (Editor’s selection of articles 2017)4. A compact LNA architecture for ultrasound transducer with record noise-power-efficiency Published in: ESSCIRC-2015, JSSC-2017(Apr.) 5. A single-cable readout IC dedicated for broadband photoacoustic probes using PVDF transducer Published in: IUS-2015(1), UMB-2016Supervised master projects: 1. The first element-level band-pass delta-sigma ADC for 2-D PZT array, employing transducer as part of the electrical loop-filter Published in: ASSCC-2017 (Best student paper), JSSC-2018(Oct.)2. A front-end ASIC for forward-looking IVUS with both high-voltage TX and reduced-wire RXPublished in: CICC-2017, JSSC-2018(May), TUFFC-20183. A mixed-signal multiplexing system for cable-reduction in ultrasound probesPublished in: IUS-2015(2)

I designed and demonstrated the first clock-free self-timed incremental sigma-delta A/D converter based on zero-crossing-detection switched-capacitor circuits, under the supervision of Dr. Michiel Pertijs. This work was presented at ISSCC 2013, San Francisco, CA.

During my bachelor thesis project at IMETU, I developed a 10-bit on-chip digital control block providing 128-channel multi-level signals for LCD driving. Results of post-layout simulation meet the specifications well. The design is realized in Chartered 0.35um 3.3V/18V mixed voltage process with full-custom design approach.

I developed and tested an on-board 16-bit sinusoidal signal generator using ROM-based Direct Digital Synthesis (DDS) technology independently. Also I investigated the FPGA realization of more advanced DDS signal generator using the CORDIC algorithm to improve the phase noise performance.