- Working with RTL team for FE quality check flows like SG-Lint, Synthesis (Fusion Compiler / Design Compiler), Conformal LEC, (RTL vs RTL/ RTL vs Netlist), fishtail(exceptions promotion and verification) and collateral generation for physical design team. - Worked on SoC RTL quality check and collateral generation to handoff to Physical Design team for implementation.- Worked on SOC RTL Lint checks to verify that RTL is aligned with Design Coding guidelines.- Worked on power-aware SoC RTL Design quality check using Synthesis.- Worked on LEC for Synthesis RTL vs Simulation RTL, RTL Vs NETLIST.- Responsible for exception promotion and verification and delivers to Physical Design team for proper timing from IP team.

- Worked on SPI Implementation for logic implementation of AESA [Active Electronically Steered Array] for seekers to perform digital operation for beam controller.- Worked on design and testing the 12 Channel SPI [1 master and 12 slaves] using hardware.- Involved in Seeker testing with newly design DSP and AESA using SPI for transferring data and receiving data from antenna.