• Developed hardware and software for FPGA communication interfaces

Design reuse is an important tool for handling complex designs, but understanding how to select and configure collections of different IPs is challenging. In my research I propose and evaluate improvements to Gaussian process models used in Bayesian optimization to more efficiently perform design-space exploration. The research touches on how to collect, compose and constrain hardware generators, such as HLS cores, and how to integrate design knowledge into the model-based optimization process.

Project Guidance:• Mentored groups of 2-4 students during weekly updates while they developed Intel/Xilinx FPGA design projects over 3 and 8-week periods. Nine such teaching assistantships were held between 2013-2018. Course Development:• Developed course assignments and materials for Xilinx FPGAs covering Vivado HLS, the MicroBlaze Ethernet subsystem and primitive inference• Developed and documented a reference design for OV5640 camera modules that used successfully in student projects.• Developed shell platform and reference designs for a convolution neural network (CNN) assignment. The platform supported partial reconfiguration of Vivado HLS-based subsystems to enable sharing of FPGAs through Linux containers and provided on-chip debug using integrated logic analyzers (ILAs), off-chip DDR4 memory support and a PCIe interface.Teaching Assistant Positions:• ECE241 - Digital Systems, 2013, 2014, 2015, 2016, 2017• ECE342 - Computer Hardware, 2014• ECE532 - Digital Systems Designs 2015, 2016, 2017, 2018• ECE1373 - Digital Design for Systems-on-Chip, 2016, 2017, 2018

• Assisted in the early development of methods and tools for integrating FPGA accelerators in the OpenCL framework for the SDAccel platform.• Supervised junior intern in their work on improving the tool interface.

• Developed an architecture for accelerating training of Viola-Jones object detectors that obtained 14-fold speed-up over multi-threaded OpenCV.• Deployed and tested on PCIe-connected Xilinx Virtex-6 FPGA development board.• Designed, verified and floorplanned scalable systolic array architecture to obtain high performance.

• Developed a high-performance multi-FPGA design for accelerating neural network (restricted Boltzmann machine) applications targeting four Xilinx Virtex-5 FPGAs and using embedded MPI.• Designed instruction-based DMA engine that allowed for memory access across FPGAs and processing engines.• Platform enabled large networks to be accelerated with flexible multi-FPGA topologies.

• Assisted in the design of new discrete graphics solutions including schematic capture, PCB layout, BOM management and measurements• Interfaced with other engineers in a cross-functional team to resolve issues including signal integrity, electromagnetic compliance and power requirements• Developed scripts in Linux and Windows automating diagnostic tests to improve the efficiency of the graphics debugging and design process