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Charles Augustine Email & Phone Number

Design Engineer@NVIDIA | Adjunct Faculty @ Georgia Tech | Circuit Design at NVIDIA
Location: Portland, Oregon, United States 15 work roles 2 schools
1 work email found @cognizant.com LinkedIn matched
✓ Verified Jun 2026 4 data sources Profile completeness 100%

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Current company
NVIDIA
Role
Design Engineer@NVIDIA | Adjunct Faculty @ Georgia Tech | Circuit Design
Location
Portland, Oregon, United States
Company size
41500 employees

Who is Charles Augustine? Overview

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Quick answer

Charles Augustine is listed as Design Engineer@NVIDIA | Adjunct Faculty @ Georgia Tech | Circuit Design at NVIDIA, a company with 41500 employees, based in Portland, Oregon, United States. AeroLeads shows a work email signal at cognizant.com and a matched LinkedIn profile for Charles Augustine.

Charles Augustine previously worked as Circuit Design Engineer at Nvidia and Adjunct Faculty at Georgia Institute Of Technology. Charles Augustine holds Ph.D., Electrical And Computer Engineering from Purdue University.

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{first}.{last}@cognizant.com
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Profile bio

About Charles Augustine

As a Staff Research Scientist at Intel Labs, my expertise in microcontrollers and computer simulations has been instrumental in advancing SRAM technologies that elevate machine learning capabilities. Our collaborative efforts have resulted in the groundbreaking development of a retention clamp for CPUs and a transformative digital current sensor for voltage regulation.In parallel, my role as Adjunct Faculty at Georgia Institute of Technology enriches the academic community with real-world insights. By bridging the gap between theory and application, we ensure our work in electrical and computer engineering not only pushes the boundaries of innovation but also serves tangible industry needs.

Listed skills include Cmos, Vlsi, Embedded Systems, Circuit Design, and 17 others.

Current workplace

Charles Augustine's current company

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NVIDIA
Nvidia
Design Engineer@NVIDIA | Adjunct Faculty @ Georgia Tech | Circuit Design
Portland, OR, US
Website
nvidia.com
Employees
41500
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15 roles

Charles Augustine work experience

A career timeline built from the work history available for this profile.

Role listed

Nvidia

Portland, OR, US

Circuit Design Engineer

Current
Nvidia

Santa Clara, CA, US

Nov 2024 - Present

Staff Research Scientist

Intel Labs

Hillsboro, OR, US

https://drive.google.com/file/d/1f6eccbziOPmWN4PzgDKCWox46yfATY1D/view?usp=sharing

Oct 2011 - Nov 2024

Conference General Co-Chair

Islped Conference
Jan 2022 - Dec 2022

Technical Program Committee Chair

Islped Conference
Jan 2021 - Jan 2022

Adjunct Faculty

Washington State University

Pullman/Spokane/Tri-Cities/Vancouver/Everett/Global, Washington, US

I currently teach a course 'Introduction to VLSI Design' (ECE-366)

Jan 2015 - Jul 2018

Graduate Research Assistant

Purdue University

West Lafayette, IN, US

Working on variation tolerant (NBTI and hard faults) and low power circuits & architectures using 65nm and 45nm technologies. Also responsible for 15nm CMOS NRI benchmarking initiative. Working on low power Sense Amplifiers and memory arrays for spin-torque magnetic memories (MRAMs). Worked on numerical modeling (NEGF and LLG) and analysis of Spintronics.

Aug 2006 - Sep 2011

Research Intern

Intel Corporation

Santa Clara, California, US

Worked on numerical modeling of various genres of magnetic tunneling junctions (MTJs) and domain wall memories based on Non Equilibrium Green’s Function (NEGF) formalism and Landau-Lifshitz-Gilbert (LLG) equation. Designed 1T-1R memories (22nm CMOS) using MTJs and analyzed them from embedded memory perspective. Worked on design of the output stage of.

May 2010 - Sep 2010

Research Intern

Freescale Semiconductor

Austin, Texas, US

Worked on developing a statistical tool (MSTAT) for estimating SRAM yield under local and global variations. Important sampling was used to develop quadratic model in order to reduce Monte Carlo simulation time.

May 2008 - Aug 2008

Design Engineer

Philips Semiconductors

Eindhoven, Noord-Brabant, NL

Worked on synthesis and timing closure of Wi-Fi chip using 90nm technology. Also responsible for developing scan architecture and ATPG & BIST analysis for the Wi-Fi chip.

Jul 2005 - Jul 2006

Design Engineer

Texas Instruments

Dallas, TX, US

Worked on developing digital cell libraries for TI’s 65nm and 90nm low power process technologies. Responsible for characterizing and developing polynomial libraries using 65nm technology.

Jun 2004 - Jul 2005

Research Intern

St Microelectronics

Geneva, Switzerland, CH

I have worked on developing a benchmarking methodology for ST7 microcontrollers considering power dissipation, performance and functionality. Work also involved emulating I2C communication protocols in ST7 micro controllers and provide recommendations for further improvements in power and performance.

Jan 2004 - Jun 2004

Research Intern

Bhabha Atomic Research Centre

IN

Worked on developing Electron Beam (EB) evaporator temperature logging system that interfaces between temperatures sensors and PC with a data card. The system can provide alerts to the users based on the temperature profile and the program can be scaled to add more sensor inputs.

May 2002 - Jul 2002
Team & coworkers

Colleagues at NVIDIA

Other employees you can reach at nvidia.com. View company contacts for 41500 employees →

BR Bhavani Reddy Bhavani Reddy Colleague at NvidiaFremont, California, United States, United States View → BK Balakrishnan K. Balakrishnan K. Colleague at NvidiaSan Francisco Bay Area, United States View → VK Vikram Kanigiri Vikram Kanigiri Colleague at NvidiaHyderabad, Telangana, India, India View → YK Yaniv Koren Yaniv Koren Colleague at NvidiaIsrael, Israel View → SS Susan Szuyin Chen Susan Szuyin Chen Colleague at NvidiaSan Francisco Bay Area, United States, United States View → RS Rishabh Sharma Rishabh Sharma Colleague at NvidiaSouth Delhi, Delhi, India, India View → CS Chaynika Saikia Chaynika Saikia Colleague at NvidiaSan Jose, California, United States, United States View → JB Jonathan Berling Jonathan Berling Colleague at NvidiaPortland, Oregon, United States, United States View → RF Ron Frimmer Ron Frimmer Colleague at NvidiaTel Aviv District, Israel, Israel View → TY Tae Yong Kim Tae Yong Kim Colleague at NvidiaSanta Clara, California, United States, United States View →
2 education records

Charles Augustine education

Ph.D., Electrical And Computer Engineering

Purdue University

Be, Electronics & Instrumentation

Birla Institute Of Technology And Science, Pilani
FAQ

Frequently asked questions about Charles Augustine

Quick answers generated from the profile data available on this page.

What company does Charles Augustine work for?

Charles Augustine works for NVIDIA.

What is Charles Augustine's role at NVIDIA?

Charles Augustine is listed as Design Engineer@NVIDIA | Adjunct Faculty @ Georgia Tech | Circuit Design at NVIDIA.

What is Charles Augustine's email address?

AeroLeads has found 1 work email signal at @cognizant.com for Charles Augustine at NVIDIA.

Where is Charles Augustine based?

Charles Augustine is based in Portland, Oregon, United States while working with NVIDIA.

What companies has Charles Augustine worked for?

Charles Augustine has worked for Nvidia, Georgia Institute Of Technology, Intel Labs, Ieee Custom Integrated Circuits Conference, and Islped Conference.

Who are Charles Augustine's colleagues at NVIDIA?

Charles Augustine's colleagues at NVIDIA include Bhavani Reddy, Balakrishnan K., Vikram Kanigiri, Yaniv Koren, and Susan Szuyin Chen.

How can I contact Charles Augustine?

You can use AeroLeads to view verified contact signals for Charles Augustine at NVIDIA, including work email, phone, and LinkedIn data when available.

What schools did Charles Augustine attend?

Charles Augustine holds Ph.D., Electrical And Computer Engineering from Purdue University.

What skills is Charles Augustine known for?

Charles Augustine is listed with skills including Cmos, Vlsi, Embedded Systems, Circuit Design, Verilog, Simulations, Microelectronics, and Very Large Scale Integration.

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