Charles Augustine

Charles Augustine Email and Phone Number

Design Engineer@NVIDIA | Adjunct Faculty @ Georgia Tech | Circuit Design @ NVIDIA
Portland, OR, US
Charles Augustine's Location
Portland, Oregon, United States, United States
Charles Augustine's Contact Details
About Charles Augustine

As a Staff Research Scientist at Intel Labs, my expertise in microcontrollers and computer simulations has been instrumental in advancing SRAM technologies that elevate machine learning capabilities. Our collaborative efforts have resulted in the groundbreaking development of a retention clamp for CPUs and a transformative digital current sensor for voltage regulation.In parallel, my role as Adjunct Faculty at Georgia Institute of Technology enriches the academic community with real-world insights. By bridging the gap between theory and application, we ensure our work in electrical and computer engineering not only pushes the boundaries of innovation but also serves tangible industry needs.

Charles Augustine's Current Company Details
NVIDIA

Nvidia

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Design Engineer@NVIDIA | Adjunct Faculty @ Georgia Tech | Circuit Design
Portland, OR, US
Website:
nvidia.com
Employees:
41500
Charles Augustine Work Experience Details
  • Nvidia
    Nvidia
    Portland, Or, Us
  • Nvidia
    Circuit Design Engineer
    Nvidia Nov 2024 - Present
    Santa Clara, Ca, Us
  • Georgia Institute Of Technology
    Adjunct Faculty
    Georgia Institute Of Technology Nov 2023 - Present
    Atlanta, Georgia , Us
  • Intel Labs
    Staff Research Scientist
    Intel Labs Oct 2011 - Nov 2024
    Hillsboro, Or, Us
    https://drive.google.com/file/d/1f6eccbziOPmWN4PzgDKCWox46yfATY1D/view?usp=sharing
  • Ieee Custom Integrated Circuits Conference
    Cicc Design Foundations Subcommittee Co-Chair
    Ieee Custom Integrated Circuits Conference Jan 2017 - Dec 2023
  • Islped Conference
    Conference General Co-Chair
    Islped Conference Jan 2022 - Dec 2022
  • Islped Conference
    Technical Program Committee Chair
    Islped Conference Jan 2021 - Jan 2022
  • Washington State University
    Adjunct Faculty
    Washington State University Jan 2015 - Jul 2018
    Pullman/Spokane/Tri-Cities/Vancouver/Everett/Global, Washington, Us
    I currently teach a course 'Introduction to VLSI Design' (ECE-366)
  • Purdue University
    Graduate Research Assistant
    Purdue University Aug 2006 - Sep 2011
    West Lafayette, In, Us
    Working on variation tolerant (NBTI and hard faults) and low power circuits & architectures using 65nm and 45nm technologies. Also responsible for 15nm CMOS NRI benchmarking initiative. Working on low power Sense Amplifiers and memory arrays for spin-torque magnetic memories (MRAMs). Worked on numerical modeling (NEGF and LLG) and analysis of Spintronics based Domain wall memories and all-spin-logic (ASL) for sub 100nm circuits.
  • Intel Corporation
    Research Intern
    Intel Corporation May 2010 - Sep 2010
    Santa Clara, California, Us
    Worked on numerical modeling of various genres of magnetic tunneling junctions (MTJs) and domain wall memories based on Non Equilibrium Green’s Function (NEGF) formalism and Landau-Lifshitz-Gilbert (LLG) equation. Designed 1T-1R memories (22nm CMOS) using MTJs and analyzed them from embedded memory perspective. Worked on design of the output stage of digital LDO.
  • Freescale Semiconductor
    Research Intern
    Freescale Semiconductor May 2008 - Aug 2008
    Austin, Texas, Us
    Worked on developing a statistical tool (MSTAT) for estimating SRAM yield under local and global variations. Important sampling was used to develop quadratic model in order to reduce Monte Carlo simulation time.
  • Philips Semiconductors
    Design Engineer
    Philips Semiconductors Jul 2005 - Jul 2006
    Eindhoven, Noord-Brabant, Nl
    Worked on synthesis and timing closure of Wi-Fi chip using 90nm technology. Also responsible for developing scan architecture and ATPG & BIST analysis for the Wi-Fi chip.
  • Texas Instruments
    Design Engineer
    Texas Instruments Jun 2004 - Jul 2005
    Dallas, Tx, Us
    Worked on developing digital cell libraries for TI’s 65nm and 90nm low power process technologies. Responsible for characterizing and developing polynomial libraries using 65nm technology.
  • St Microelectronics
    Research Intern
    St Microelectronics Jan 2004 - Jun 2004
    Geneva, Switzerland, Ch
    I have worked on developing a benchmarking methodology for ST7 microcontrollers considering power dissipation, performance and functionality. Work also involved emulating I2C communication protocols in ST7 micro controllers and provide recommendations for further improvements in power and performance.
  • Bhabha Atomic Research Centre
    Research Intern
    Bhabha Atomic Research Centre May 2002 - Jul 2002
    In
    Worked on developing Electron Beam (EB) evaporator temperature logging system that interfaces between temperatures sensors and PC with a data card. The system can provide alerts to the users based on the temperature profile and the program can be scaled to add more sensor inputs.

Charles Augustine Skills

Cmos Vlsi Embedded Systems Circuit Design Verilog Simulations Microelectronics Very Large Scale Integration Computer Architecture Cadence Virtuoso Logic Synthesis Integrated Circuit Design Processors Timing Closure Cadence Photolithography Modelsim Analog Circuit Design Sensors Microcontrollers Device Characterization

Charles Augustine Education Details

  • Purdue University
    Purdue University
    Electrical And Computer Engineering
  • Birla Institute Of Technology And Science, Pilani
    Birla Institute Of Technology And Science, Pilani
    Electronics & Instrumentation

Frequently Asked Questions about Charles Augustine

What company does Charles Augustine work for?

Charles Augustine works for Nvidia

What is Charles Augustine's role at the current company?

Charles Augustine's current role is Design Engineer@NVIDIA | Adjunct Faculty @ Georgia Tech | Circuit Design.

What is Charles Augustine's email address?

Charles Augustine's email address is au****@****ail.com

What schools did Charles Augustine attend?

Charles Augustine attended Purdue University, Birla Institute Of Technology And Science, Pilani.

What skills is Charles Augustine known for?

Charles Augustine has skills like Cmos, Vlsi, Embedded Systems, Circuit Design, Verilog, Simulations, Microelectronics, Very Large Scale Integration, Computer Architecture, Cadence Virtuoso, Logic Synthesis, Integrated Circuit Design.

Who are Charles Augustine's colleagues?

Charles Augustine's colleagues are Mykola Yatsyshyn, Brian Gaeke, Siddharth Maharana, Lakshman Kishore, Imad Aljundi, Mervat Khoury Daoud, Andrea (Andi) Mcpadden.

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