● Architected, implemented and verified Transport Layer Security (TLS) 1.3 IP● Led the design of a 10Gbps Ethernet datapath with Layer 2-4 processing● Developed a common system verilog class-based test bench for use across multiple projects● Deployed randomized vector stimulus to root out corner-cases and increase code coverage● Built modular AXI-STREAM library for code reuse● Integrated and verified third party encryption and cryptography IP● Incorporated simulation and build environments into GitLab CI● Authored DirectStream’s HDL design guidelines, focusing on industry best practices

● Proven leader tasked with multiple challenges, including manufacturing issues, third party integration and release code management● Integrated IP security (IPsec) IP into an avionics platform● Led effort using Xilinx SDK to debug slow SPI transfer performance, resulting in 5x improvement● Upgraded build environment to include Make and Jenkins CI pipeline scripts● Member of FPGA process development team

Principal Hardware Engineer 2015-2018, Senior Hardware Engineer 2010-14, Hardware Engineer 2005-09, Associate Hardware Engineer 2004● Member of the NG-PON2 development team slated for deployment by Verizon as their nextgeneration fiber optic network● Team lead for Verizon site lab qualification testing● Led effort to identify and reduce power consumption by ~20% on NG-PON2/XGSPON products● Lead developer for 3 NG-PON2/XGSPON products, using modular coding for code reuse● Implemented PCIE tandem loading on multiple platforms● Led the design of the 811NG ONU product datapath which included SPI configuration for10Gbps datapath with packet lookups, DDR3 buffer, and Ethernet MAC/PHY● Wrote architecture design documentation for the Calix GPON-16 product● Main FPGA designer for flagship E7-2 GPON product● Experienced with external memories including TCAM, QDRII, RLDRAMII, DDR3● Demonstrated ability to design reliable products - multiple designs with 10,000+ units sold