Chase Cook Email and Phone Number

Managed a team of Product and Test engineers and managers responsible for new product development, from pre-silicon engagement and device definition, through PG, bring-up, characterization, qualification, and production release** Drove design engagements, hardware, software, and design-for-test strategies enabling max-multisite solutions and best-in-class Cost-of-Test for latest TI-Processor grade automotive devices** Increased design-for-test (DfT) strategies to enable ATE hardware simplification, reduction of complex on-board circuits; further contributing to reduced hardware costs and higher first-pass success.** Benchmark Cost-of-Test (COT) as a percentage of die-Cost. Drove DfT and test-strategies to enable new levels of COT. ** Successfully realized COT reduction to benchmark levels across process nodes. ** Enabled through max-multisite DfT architecture, probe-maximized test-coverage (cold/hot), and detailed characterization efforts enabling high-quality, optimized, robust production test-flows** Responsible for managing resourcing, budgeting, and execution timelines across multiple projects, and coordinating with all cross-functional teams to assure all business requirements are scoped and met** Defined and executed streamlined NPDE execution strategies, milestones, and metrics enabling cycle-time reduction of PG-to-Production** Defined and drove qualification strategies at a platform / family / technology level focused on maximizing qualification by similarity methodology** Drive maximum re-use across product families; IP-reuse, qualified package reuse** Enables reduced qualification complexities and cycle-times; accelerate back-end execution and path to release-to-production. ** Realized and sustained reduction in ATE/qual hardware costs to benchmark levels for both core and spin product definitions.

Managed multiple teams of Product and Test engineers and managers; supporting cost-of-goods-sold (COGS) and sustaining activities for all devices and programs within BU. Supported products across multiple technology nodes from 65nm down to 16nm within the scope of this portfolio** Defined benchmark execution timelines, scorecard metrics, and milestones enabling full device entitlement Post-Release-to-Production within RTP+2Qs** Piloted RTM-at-Entitlement process and metrics (requirements defined at project kickoff; gating release to production) to assure clear path to entitlement for sustaining teams; Yield, Test-Cost, DfT, Multisite, Test-Coverage, Quality** Responsible for continually analyzing and identifying largest entitlement gaps and defining priority projects to address** Owned defining, tracking, summarizing and presenting to Business Unit management Monthly / Quarterly COGs $-Savings impact, ** Subsequent impact of these efforts resulting in capacity savings of ATE testers, handlers, and burn-in ovens.** Responsible for all factory interface for post-production support, capacity forecast and obtainment, excursions and customer support** Responsible for all customer return engagements, device analysis, and management through FA pipelines with disposition, resolution, or corrective actions, while maintaining defined cycle-time metrics** Drove a focused Quality-Improvement and DPPM reduction initiative across TIs high-volume 28nm platform portfolio, reducing DPPM across automotive products.** Deep-Dive analysis on top return fail modes and commonalities. Enhanced Probe and Final-Test outlier schemes. Improved statistical outlier analysis and real-time data processing / outlier detection. Optimized Statistical Bin-Limits and surround-by detection.** Defined and drove several new initiatives to improve factory capacity and throughput via burn-in optimizations and transition of cold/hot temp testing from packaged level to wafer probe solution

Worked cross-functionally with project management, planning, quality, failure analysis, design, and other product engineering teams to meet project goals and deliverables; while maintaining timeline for release to production and volume ramp** Heavily involved with device bring-up from early planning phase through production volume ramp of >10 automotive grade products targeting a variety of both industrial and automotive end applications. ** Direct contributions across 65nm/45nm/28nm nodes** Lead engineer productizing products ranging from low-power (<2watts) <25mm2 die, to high-power (>26watts), >200mm2 die-sizes requiring unique temperature control capable of large volume, sustainable production** Lead bring-up engineer driving tester platform transitions from legacy platform to latest Advantest V93K and Teradyne UFlex+ platforms; have driven and executed multiple characterization, qual, and production offloads, with continued production support through customer volume ramp phases** Responsible for defining and implementing production quality test-flows meeting automotive-grade DPPM, while also achievingTest-Cost and yield targets defined at kickoff phase for each project; achieving entitlement milestones and metrics for each product** Direct experience implementing and debugging across multiple common IP, including SRAM, SRAM repair, Serdes, DDR, HSIOs, ADC/DAC, USB** Have characterized, optimized and implemented various techniques of Adaptive-Voltage-Scaling (AVS), enabling performance-based scaling, as well as power-based scaling** Support multiple automotive grade (Q100/Q006) qualification executions** Worked extensively with packaging team on cutting-edge flip chip packaging technologies including nFBGA, Cu Pillar, Au Stud Bump, POP, Bump, Wire-bond as well as the specific test and reliability requirements for each