R&D Engineer Ii
• Implemented optimizations for System Verilog/VHDL compiler and simulator (VCS) using C++.• Conducted analysis of CPU time and memory consumption bottlenecks, and proposed optimization solutions, resulting in a performance increase of 11x over the original system and 1.5x faster than the nearest competitor.• Collaborated with customers to troubleshoot race conditions and simulation mismatches using Verdi.• Developed test cases for system regression testing to ensure stability and functionality.• Identified and resolved memory leak issues in VCS using Valgrind.• Earned a Spot Bonus two months after onboarding for addressing critical defects in the Verilog compiler.